Recent advances in test planning for modular testing of core-based SOCs

Proceedings of the Asian Test Symposium

Volumn 2002-January, Issue , 2002, Pages 320-325

  Iyengar, V ^a   Chakrabarty, K ^b   Marinissen, E J ^c  

^a IBM MICROELECTRONICS   (United States)

^b DUKE UNIVERSITY   (United States)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Costs; Design optimization; Hip; Laboratories; Logic testing; Microelectronics; Pins; System testing; System on a chip; Wires

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COSTS; HOT ISOSTATIC PRESSING; LABORATORIES; MICROELECTRONICS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; WIRE;

DESIGN OPTIMIZATION; LOGIC TESTING; PINS; SYSTEM ON A CHIP; SYSTEM TESTING;

SYSTEM-ON-CHIP;

EID: 84949754675     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2002.1181731     Document Type: Conference Paper

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