Test bus sizing for system-on-a-chip

IEEE Transactions on Computers

Volumn 51, Issue 5, 2002, Pages 449-459

  Iyengar, Vikram ^a,b   Chakrabarty, Krishnendu ^a,b  

^a IEEE   (United States)

^b Duke University   (United States)

Author keywords

Core based systems; Embedded core testing; Integer linear programming; Linearization; Test access mechanism (TAM); Test bus; Testing time

Indexed keywords

CORE BASED SYSTEMS; EMBEDDED CORE TESTING; INTEGER LINEAR PROGRAMMING; SYSTEM ON A CHIP; TEST ACCESS MECHANISM; TEST BUS SIZING;

BUILT-IN SELF TEST; COMPUTER SIMULATION; INTEGER PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LINEAR PROGRAMMING; LINEARIZATION;

COMPUTER CIRCUITS;

EID: 0036566158     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2002.1004585     Document Type: Article

References (13)

1. Scan chain design for test time reduction in core-based ICs
2. Design of system-on-a-chip test access architectures using integer linear programming
3. Design of system-on-a-chip test access architectures under place-and-route and power constraints
4. P1500 benchmarking task force chair
5. A fast and low cost testing technique for core-based system-on-chip
6. Testing re-usable IP: A case study
7. Direct access test scheme-design of block and core cells for embedded ASICs
8. A structured and scalable mechanism for test access to embedded reusable cores
9. Wrapper design for embedded core test
10. Using partial isolation rings to test core-based designs
11. A structured test re-use methodology for core-based system chips