Test economics for multi-site test with modern cost reduction techniques

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 411-416

  Volkerink, E H ^a   Khoche, A ^a   Rivoir, J ^a   Hilliges, K D ^a  

^a AGILENT LABORATORIES   (United States)

Author keywords

Bandwidth; Circuit testing; Cost benefit analysis; Frequency; Integrated circuit technology; Laboratories; Pins; Scalability; System testing; USA Councils

Indexed keywords

BANDWIDTH; COMMERCE; COST EFFECTIVENESS; COST REDUCTION; COSTS; ECONOMICS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT TESTING; LABORATORIES; SCALABILITY; VLSI CIRCUITS;

CIRCUIT TESTING; FREQUENCY; INTEGRATED CIRCUIT TECHNOLOGY; PINS; SYSTEM TESTING; USA COUNCILS;

COST BENEFIT ANALYSIS;

EID: 0012082866     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011173     Document Type: Conference Paper

References (9)

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