On concurrent test of core-based SOC design

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 4-5, 2002, Pages 401-414

  Huang, Yu ^a   Cheng, Wu Tung ^a   Tsai, Chien Chung ^a   Mukherjee, Nilanjan ^a   Samman, Omer ^a   Zaidan, Yahya ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

2 dimensional bin packing; Concurrent SOC test; Pin mapping; Test scheduling

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; RESOURCE ALLOCATION; SCHEDULING;

CONCURRENT TEST; POWER CONSUMPTION; SYSTEM ON CHIP; TEST ACCESS MECHANISM; TEST SCHEDULING;

INTEGRATED CIRCUIT TESTING;

EID: 0036693158     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1016541407006     Document Type: Article

References (23)

1. A novel strategy to test core based designs
2. Test scheduling for core-based systems using mixed-integer linear programming
3. Design of system-on-a-chip test access architectures using integer linear programming
4. Design of system-on-a-chip test access architectures under place-and-route and power constraints
5. Performance bounds for level-oriented two-dimensional packing algorithms
6. Multi-tiered algorithms for 2-dimensional bin packing
7. A fast and low-cost testing technique for core-based system-chips
8. A low overhead design for testability and test generation technique for core-based system-on-a-chip
9. Direct access test scheme-Design of block and core cells for embedded ASICs
10. Test protocol scheduling for embedded core-based system ICs
11. A structured and scalable mechanism for test access to embedded reusable cores
12. Low cost testing of system-on-chip
13. An ILP formulation to optimize test access mechanism in system-on-chip testing
14. Simultaneous module selection and scheduling for power-constrained testing of core based systems
15. A polynomial-time algorithm for power constrained testing of core based systems
16. A novel test methodology for core-based system LSIs and a testing time minimization problem
17. Testing embedded cores using partial isolation rings
18. A structured test re-use methodology for core-based system chips
19. An IEEE 1149.1 based test access architecture for ICs with embedded IP cores
20. Addressable test ports an approach to testing embedded cores
21. Test requirement for embedded core-based systems and IEEE P1500
22. Testing embedded core-based system chips