Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 1159-1168

  Iyengar, Vikram ^a   Goel, Sandeep Kumar ^b   Marinissen, Erik Jan ^b   Chakrabarty, Krishnendu ^c  

^a IBM MICROELECTRONICS   (United States)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c Duke University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; BENCHMARKING; CONSTRAINT THEORY; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; OPTIMIZATION; RESOURCE ALLOCATION;

AUTOMATIC TESTING EQUIPMENT; MULTI-SITE TESTING; SYSTEM ON CHIP; TEST ACCESS MECHANISMS; TEST RESOURCE OPTIMIZATION;

INTEGRATED CIRCUIT TESTING;

EID: 0036443126     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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