Defect-oriented test scheduling

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 433-438

  Jiang, Wanli ^a   Vinnakota, Bapiraju ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL INTEGRATED CIRCUITS; HEURISTIC METHODS; INTEGER PROGRAMMING; LINEAR INTEGRATED CIRCUITS; POLYNOMIALS; VLSI CIRCUITS;

ANALOG INTEGRATED CIRCUITS; DEFECT ORIENTED TEST SCHEDULING HEURISTIC; ORDERING ALGORITHM;

INTEGRATED CIRCUIT TESTING;

EID: 0032664178     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (8)