Resource allocation and test scheduling for concurrent test of core-based SOC design

Proceedings of the Asian Test Symposium

Volumn , Issue , 2001, Pages 265-270

  Huang, Yu ^a   Cheng, Wu Tung ^b   Tsai, Chien Chung ^b   Mukherjee, Nilanjan ^b   Samman, Omer ^b   Zaidan, Yahya ^b   Reddy, Sudhakar M ^a  

^a The University of Iowa   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; OPTIMIZATION; PROBLEM SOLVING; RESOURCE ALLOCATION; SCHEDULING;

CONCURRENT TEST; CORE-BASED SYSTEM-ON-CHIP DESIGN; TEST ACCESS MECHANISM; TEST SCHEDULING;

INTEGRATED CIRCUIT TESTING;

EID: 0035701545     PISSN: 10817735     EISSN: None     Source Type: Journal    
DOI: 10.1109/ATS.2001.990293     Document Type: Article

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