A fast and low cost testing technique for core-based system-on-chip

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 542-547

  Ghosh, Indradeep ^a   Dey, Sujit ^b   Jha, Niraj K ^a  

^a Princeton University   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COST REDUCTION; ECONOMIC AND SOCIAL EFFECTS; PROGRAMMABLE LOGIC CONTROLLERS; TRANSPARENCY; COST EFFECTIVENESS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS;

AREA OVERHEAD; CORE BASED SYSTEM ON CHIPS; EMBEDDED CORES; LOW COST TESTING; REDUCTION IN AREA; SIMULTANEOUS REDUCTION; TEST APPLICATION TIME; TRANSPARENCY PROPERTIES;

SYSTEM-ON-CHIP; MICROPROCESSOR CHIPS;

SYSTEM-ON-CHIPS (SOC);

EID: 0031623034     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277190     Document Type: Conference Paper

References (11)

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