On using rectangle packing for SOC wrapper/TAM co-optimization

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 253-258

  Iyengar, V ^a   Chakrabarty, K ^a   Marinissen, E J ^b  

^a Duke University   (United States)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Benchmark testing; Design engineering; Design optimization; Integer linear programming; Laboratories; Logic testing; Pins; System testing; System on a chip; Wires

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; DISTRIBUTED COMPUTER SYSTEMS; INDUCTIVE LOGIC PROGRAMMING (ILP); INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT TESTING; LABORATORIES; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; TESTING; WIRE;

BENCHMARK TESTING; DESIGN ENGINEERING; DESIGN OPTIMIZATION; INTEGER LINEAR PROGRAMMING; LOGIC TESTING; PINS; SYSTEM ON A CHIP; SYSTEM TESTING;

INTEGER PROGRAMMING;

EID: 13244280761     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011146     Document Type: Conference Paper

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