Cluster-based test architecture design for system-on-chip

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 259-264

  Goel, S K ^a   Marinissen, E J ^a  

^a IC Design Digital Design Test   (Netherlands)

Author keywords

Benchmark testing; Circuit testing; Computer industry; Costs; Digital integrated circuits; Integrated circuit testing; Laboratories; Semiconductor device testing; System testing; System on a chip

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLUSTER COMPUTING; COMPUTER ARCHITECTURE; COMPUTER TESTING; COSTS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; LABORATORIES; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; SYSTEM-ON-CHIP; VLSI CIRCUITS;

BENCHMARK TESTING; CIRCUIT TESTING; COMPUTER INDUSTRY; SYSTEM ON A CHIP; SYSTEM TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0002515893     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011147     Document Type: Conference Paper

References (12)

1. Yervant Zorian, Erik Jan Marinissen, and Sujit Dey. Testing Embedded-Core Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 130-143, Washington, DC, October 1998.
2. Erik Jan Marinissen and Yervant Zorian. Challenges in Testing Core-Based System ICs. IEEE Communications Magazine, 37(6):104-109, June 1999.
3. Erik Jan Marinissen, Rohit Kapur, and Yervant Zorian. On Using IEEE P1500 SECT for Test Plug-n-Play. In Proceedings IEEE International Test Conference (ITC), pages 770-777, Atlantic City, NJ, October 2000.
4. Joep Aerts and Erik Jan Marinissen. Scan Chain Design for Test Time Reduction in Core-Based ICs. In Proceedings IEEE International Test Conference (ITC), pages 448-457, Washington, DC, October 1998.
5. Krishnendu Chakrabarty. Design of System-on-a-Chip Test Access Architectures Using Integer Linear Programming. In Proceedings IEEE VLSI Test Symposium (VTS), pages 127-134, Montreal, Canada, April 2000.
6. Sandeep Kumar Goel and Erik Jan Marinissen. TAM Architectures and Their Implication on Test Application Time. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 3.3-1-10, Marina del Rey, CA, May 2001.
7. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores. Journal of Electronic Testing: Theory and Applications, 18(2):211-228, April 2002.
8. Prab Varma and Sandeep Bhatia. A Structured Test Re-Use Methodology for Core-Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 294-302, Washington, DC, October 1998.
9. Krishnendu Chakrabarty. Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 432-437, Los Angeles, CA, June 2000.
10. Erik Jan Marinissen, Sandeep Kumar Goel, and Maurice Lousberg. Wrapper Design for Embedded Core Test. In Proceedings IEEE International Test Conference (ITC), pages 911-920, Atlantic City, NJ, October 2000.
11. Erik Jan Marinissen, Vikram Iyengar, and Krishnendu Chakrabarty. ITC'02 SOC Test Benchmarks Web Site. http://www.extra.research.philips.com/itc02socbench/.
12. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Efficient Wrapper/TAM Co-Optimization for Large SOCs. In Proceedings Design, Automation, and Test in Europe (DATE), Paris, France, March 2002.