OPMISR: The foundation for compressed ATPG vectors

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 748-757

  Barnhart, Carl ^a   Brunkhorst, Vanessa ^a   Distler, Frank ^a   Farnsworth, Owen ^a   Keller, Brion ^a   Koenemann, Bernd ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; BUFFER STORAGE; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT MANUFACTURE;

AUTOMATIC TEST PATTERN GENERATION (ATPG);

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0035687658     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966696     Document Type: Article

References (23)

1. Low-cost testing of high-density logic components
2. Self-testing of multichip logic modules
3. Built-in self test support in the IBM engineering design system
4. Logic BIST for large industrial designs: Real issues and case studies
5. A method for generating weighted random test patterns
6. Test vector compression via cyclical scan chains and its application to testing core-based designs
7. Virtual scan chains: A means for reducing scan length in cores
8. Reducing test data volume using external/LBIST hybrid test patterns
9. Test volume and application time reduction through scan chain concealment
10. Using on-chip test pattern compression for full scan SoC design
11. Efficient test data compression and decompression for system-on-a-chip using internal scan chain and golomb coding
12. Scan test improvement with synthesized MISR
13. Logic DFT and test resource partitioning for 100M gate ASICs
14. OPMISR: Accelerated scan with on-product signatures
15. Diagnosis of BIST failures by PPSFP simulation
16. LFSR-coded test patterns for scan designs
17. Standard test interface language (STIL) for digital test vector data - Language manual
18. Test methodologies and design automation for IBM ASICs