On test scheduling for core-based SOCs

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 505-510

  Koranne, S ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DATA COMPRESSION; DESIGN; EMBEDDED SYSTEMS; GRAPH THEORY; INTEGER PROGRAMMING; INTEGRATED CIRCUIT TESTING; POLYNOMIAL APPROXIMATION; POLYNOMIALS; PROGRAMMABLE LOGIC CONTROLLERS; SCHEDULING; SYSTEM-ON-CHIP;

CORE BASED SYSTEM ON CHIPS; GRAPH-THEORETIC PROBLEM; INTEGER LINEAR PROGRAMMING; MINIMUM MAKESPAN; POLYNOMIAL-TIME; TEST ACCESS ARCHITECTURE; TEST ACCESS MECHANISM; TEST SCHEDULING;

TESTING;

EID: 84962242740     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994970     Document Type: Conference Paper

References (18)

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