A novel test time reduction algorithm for test architecture design for core-based system chips

Proceedings of the European Test Workshop

Volumn 2002-January, Issue January, 2002, Pages 7-12

  Goel, Sandeep Kumar ^a   Marinissen, Erik Jan ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; HEURISTIC ALGORITHMS; INTEGRATED CIRCUITS; SYSTEM-ON-CHIP; TESTING;

CORE INTERNAL; MEMORY DEPTH; SOC TESTS; TEST APPLICATION TIME; TEST ARCHITECTURE; TEST TIME REDUCTION; WRAPPER DESIGN;

INTEGRATED CIRCUIT DESIGN;

EID: 2542506028     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2002.1029633     Document Type: Conference Paper

References (17)

1. Erik Jan Marinissen and Yervant Zorian. Challenges in Testing Core-Based System ICs. IEEE Communications Magazine, 37(6):104-109, June 1999.
2. Yervant Zorian, Erik Jan Marinissen, and Sujit Dey. Testing Embedded-Core Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 130-143, Washington, DC, October 1998.
3. Erik Jan Marinissen, Vikram Iyengar, and Krishnendu Chakrabarty. ITC'02 SOC Test Benchmarks Web Site. http://www.extra.research.philips.com/itc02socbench/.
4. Joep Aerts and Erik Jan Marinissen. Scan Chain Design for Test Time Reduction in Core-Based ICs. In Proceedings IEEE International Test Conference (ITC), pages 448-457, Washington, DC, October 1998.
5. Prab Varma and Sandeep Bhatia. A Structured Test Re-Use Methodology for Core-Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 294-302, Washington, DC, October 1998.
6. Erik Jan Marinissen et al. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores. In Proceedings IEEE International Test Conference (ITC), pages 284-293, Washington, DC, October 1998.
7. Krishnendu Chakrabarty. Design of System-on-A-Chip Test Access Architectures Using Integer Linear Programming. In Proceedings IEEE VLSI Test Symposium (VTS), pages 127-134, Montreal, Canada, April 2000.
8. Zahra sadat Ebadi and Andre Ivanov. Design of an Optimal Test Access Architecture Using a Genetic Algorithm. In Proceedings IEEE Asian Test Symposium (ATS), pages 205-210, Kyoto, Japan, November 2001.
9. Krishnendu Chakrabarty. Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 432-437, Los Angeles, CA, June 2000.
10. Yu Huang et al. Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design. In Proceedings IEEE Asian Test Symposium (ATS), pages 265-270, Kyoto, Japan, November 2001.
11. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores. Journal of Electronic Testing: Theory and Applications, 18(2):213-230, April 2002.
12. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Efficient Wrapper/TAM Co-Optimization for Large SOCs. In Proceedings Design, Automation, and Test in Europe (DATE), Paris, France, March 2002.
13. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. In Proceedings IEEE VLSI Test Symposium (VTS), pages 253-258, Monterey, CA, April 2002.
14. Sandeep Kumar Goel and Erik Jan Marinissen. Cluster-Based Test Architecture Design for System-on-Chip. In Proceedings IEEE VLSI Test Symposium (VTS), pages 259-264, Monterey, CA, April 2002.
15. Erik Jan Marinissen, Sandeep Kumar Goel, and Maurice Lousberg. Wrapper Design for Embedded Core Test. In Proceedings IEEE International Test Conference (ITC), pages 911-920, Atlantic City, NJ, October 2000.
16. R.L. Graham. Bounds on Multiprocessing Anomalies. SIAM Journal of Applied Mathematics, 17:416-429, 1969.
17. E.G. Coffman Jr., M.R. Garey, and D.S. Johnson. An Application of Bin-Packing to Multiprocessor Scheduling. SIAM Journal of Computing, 7(1):1-17, February 1978.