On IEEE P1500's standard for embedded core test

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 4-5, 2002, Pages 365-383

  Marinissen, Erik Jan ^a   Kapur, Rohit ^b   Lousberg, Maurice ^a   McLaurin, Teresa ^c   Ricchetti, Mike ^d   Zorian, Yervant ^e  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b SYNOPSYS INC   (United States)

^c ARM Inc   (United States)

^d Intellitech Corp   (United States)

^e LogicVision Inc   (United States)

Author keywords

Compliance levels; Core test language; Core test wrapper; Embedded cores; Standardization

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; INTEROPERABILITY; MATHEMATICAL MODELS; STANDARDIZATION;

CORE TEST LANGUAGE; EMBEDDED CORE TEST; SCALABLE WRAPPER ARCHITECTURE;

INTEGRATED CIRCUIT TESTING;

EID: 0036693092     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1016585206097     Document Type: Article

References (27)

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