Efficient Wrapper/TAM co-optimization for large SOCs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 491-498

  Iyengar, Vikram ^a   Chakrabarty, Krishnendu ^a   Marinissen, Erik Jan ^b  

^a Duke University   (United States)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

EXHAUSTIVE ENUMERATION; HEURISTIC TECHNIQUES; INTEGER LINEAR PROGRAMMING; ORDERS OF MAGNITUDE; SYSTEM-ON-CHIP TEST; TAM OPTIMIZATION; TEST ACCESS ARCHITECTURE; TEST ACCESS MECHANISM;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EXHIBITIONS; HEURISTIC ALGORITHMS; HEURISTIC METHODS; INTEGER PROGRAMMING;

DESIGN;

EID: 84893718115     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998318     Document Type: Conference Paper

References (15)

1. J. Aerts and E.J. Marinissen. Scan chain design for test time reduction in core-based ICs. Proc. Int. Test Conf., pp. 448-457, 1998.
2. M. Berkelaar. lpsolve 3.0, Eindhoven University of Technology, Eindhoven, The Netherlands. ftp://ftp.ics.ele.tue.nl/pub/lp.solve
3. P. Brucker. Scheduling Algorithms. 3rd ed., Springer, Berlin, Germany, 2001.
4. K. Chakrabarty. Design of system-on-a-chip test access architectures under place-and-route and power constraints. Proc. Design Automation Conf., pp. 432-437, 2000.
5. K. Chakrabarty. Optimal test access architectures for system-on-a-chip. ACM Trans. Design Automation of Electronic Systems, vol. 6, pp. 26-49, January 2001.
6. M.R. Garey and D.S. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness.W.H. Freeman and Co., San Francisco, CA, 1979.
7. J. Hromkovic. Algorithmics for Hard Problems. Springer, Berlin, Germany, 2001.
8. V. Iyengar, K. Chakrabarty, and E.J. Marinissen. Test wrapper and test access mechanism co-optimization for system-on-chip. J. Electronic Testing: Theory and Applications, vol. 18, March 2002, in print.
9. E. Larsson and Z. Peng. An integrated system-on-chip test framework. Proc. Design, Automation, and Test in Europe (DATE), pp. 138-144, 2001.
10. J.H. van Lint and R.M.Wilson, A Course in Combinatorics, Cambridge University Press, 1992.
11. E.J. Marinissen et al. A structured and scalable mechanism for test access to embedded reusable cores. Proc. Int. Test Conf., pp. 284-293, 1998.
12. E.J. Marinissen, S.K. Goel and M. Lousberg. Wrapper design for embedded core test. Proc. Int. Test Conf., pp. 911-920, 2000.
13. M. Nourani and C. Papachristou. An ILP formulation to optimize test access mechanism in system-on-chip testing. Proc. Int. Test Conf., pp. 902-910, 2000.
14. P. Varma and S. Bhatia. A structured test re-use methodology for corebased system chips. Proc. Int. Test Conf., pp. 294-302, 1998.
15. Y. Zorian, E.J. Marinissen and S. Dey. Testing embedded-core-based system chips. IEEE Computer, vol. 32, pp. 52-60, June 1999.