System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 9, 2002, Pages 1088-1094

  Iyengar, Vikram ^a,b   Chakrabarty, Krishnendu ^a  

^a Duke University   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

Core based systems; Embedded core testing; Mixed integer linear programming; Open shop schedules; Precedence constraints; Preemptive test scheduling

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; FLIP FLOP CIRCUITS; HEURISTIC METHODS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; MATHEMATICAL MODELS; POLYNOMIALS; SCHEDULING;

CORE-BASED SYSTEM; EMBEDDED CORE TESTING; HEURISTIC ALGORITHM; MIXED INTEGER LINEAR PROGRAMMING; OPEN SHOP SCHEDULE; PREEMPTIVE TEST SCHEDULING; SYSTEM-ON-A-CHIP TEST;

BUILT-IN SELF TEST;

EID: 0036736274     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.801102     Document Type: Article

References (15)

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