Using partial isolation rings to test core-based designs

IEEE Design and Test of Computers

Volumn 14, Issue 4, 1997, Pages 52-59

  Touba, Nur A ^a,b,c,d,e   Pouya, Bahram ^a,b,e,f  

^a UNIVERSITY OF TEXAS   (United States)

^b The University of Texas at Austin   (United States)

^c UNIVERSITY OF MINNESOTA   (United States)

^d STANFORD UNIVERSITY   (United States)

^e IEEE   (United States)

^f UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); LOGIC DESIGN; MULTIPLEXING EQUIPMENT; SYSTEMS ANALYSIS;

AUTOMATIC TEST PATTERN GENERATION; CORE INTERFACES; DESIGN FOR TESTABILITY METHOD; PARTIAL ISOLATION RINGS; USER DEFINED LOGIC;

INTEGRATED CIRCUIT TESTING;

EID: 0031249773     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.632881     Document Type: Article

References (5)

1. V. Immaneni and S. Raman, "Direct Access Test Scheme - Design of Block and Core Cells for Embedded ASICs," Proc. Int'l Test Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1990, pp. 488-492.
2. K. Chakrabarty and J.P. Hayes, "Efficient Test Response Compression for Multiple-Output Circuits," Proc. Int'l Test Conf., IEEE CS Press, 1994, pp. 501-510.
3. M.H. Konijnenburg, J.T. van der Linden, and A.J. van de Goor, "Test Pattern Generation with Restrictors," Proc. Int'l Test Conf., IEEE CS Press, 1993, pp. 598-605.
4. M.H. Konijnenburg, J.T. van der Linden, and A.J. van de Goor, "Automatic Test Pattern Generation for Industrial Circuits with Restrictors," Microelectronics J., Vol. 26, No. 7, Oct. 1995, pp. 598-605.
5. P. Wohl, and J. Waicukauski, "Test Generation for Ultra-Large Circuit Using ATPG Constraints and Test-Pattern Templates," Proc. Int'l Test Conf., IEEE CS Press, 1996, pp. 13-20.