Optimal test access architectures for system-on-a-chip

ACM Transactions on Design Automation of Electronic Systems

Volumn 6, Issue 1, 2001, Pages 26-49

  Chakrabarty, Krishnendu ^a  

^a DUKE UNIVERSITY   (United States)

Author keywords

Design; Reliability

Indexed keywords

EID: 0012157888     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/371254.371258     Document Type: Article

References (22)

1. AERTS, J. AND MARINISSEN, E. J. 1998. Scan chain design for test time reduction in core-based ICs. In Proceedings of the International Test Conference. IEEE Computer Society Press, Los Alamitos, CA, 448-457.
2. BERKELAAR, M. 1999. Ipsolve, version 2.0. Department of Mathematics and Computing Science, Eindhoven University of Technology, Eindhoven, Netherlands. michel@es.ele.tue.nl
3. BRGLEZ, F., BRYANT, D., AND KOZMINSKI, K. 1989. Combinational profiles of sequential benchmark circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems (Portland, OR, May). IEEE Press, Piscataway, NJ, 1929-1934.
4. BRGLEZ, F. AND FUJIWARA, H. 1985. A neural netlist of 10 combinational benchmark circuits and a target translator in Fortran. In Proceedings of IEEE International Symposium on Circuits and Systems. IEEE Computer Society, Washington, DC, 695-698.
5. CHAKRABARTY, K. 2000a. Test scheduling for core-based systems using mixed-integer linear programming. IEEE Trans. Comput.-Aided Des. 19, 10 (Oct.), 1163-1174.
6. CHAKRABARTY, K. 2000b. Design of system-on-a-chip test access architectures under place-and-route and power constraints. In Proceedings of the Conference on Design Automation (DAC '2000). ACM Press, New York, NY, 432-437.
7. CHAKRABARTY, K. 1999. Test scheduling for core-based systems. In Proceedings of International Conference on Computer-Aided Design (Nov.). IEEE Computer Society Press, Los Alamitos, CA, 391-394.
8. FOURER, R., GAY, D. M., AND KERNIGHAN, B. W. 1993. AMPL: A Modeling Language for Mathematical Programming. Duxbury Press, Boston, MA.
9. GAMS DEVELOPMENT CORPORATION. 1993. GAMS: A User's Guide. Boyd and Fraser Publishing Co., Danvers, MA.
10. GAREY, M. AND JOHNSON, D. 1979. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman and Co., New York, NY.
11. GHOSH, I., DEY, S., AND JHA, N. K. 1998. A fast and low cost testing technique for core-based system-on-chip. In Proceedings of the 35th Annual Conference on Design Automation (DAC '98, San Francisco, CA, June 15-19), B. R. Chawla, R. E. Bryant, and J. M. Rabaey, Chairs. ACM Press, New York, NY, 542-547.
12. GHOSH, I., JHA, N. K., AND DEY, S. 1997. A low overhead design for testability and test generation technique for core-based systems. In Proceedings of the International Test Conference. IEEE Computer Society Press, Los Alamitos, CA, 50-59.
13. HAMZAOGLU, I. AND PATEL, J. H. 1998. Test set compaction algorithms for combinational circuits. In Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '98, San Jose, CA, Nov. 8-12), H. Yasuura, Chair. ACM Press, New York, NY, 283-289.
14. IMMANENI, V. AND RAMAN, S. 1990. Direct access test scheme: Design of block and core cells for embedded ASICs. In Proceedings of the International Test Conference. IEEE Computer Society Press, Los Alamitos, CA, 488-492.
15. MARINISSEN, E. J. AND LOUSBERG, M. 1999. The role of test protocols in testing embedded-core-based system ICs. In Proceedings of the IEEE European Test Workshop. IEEE Computer Society Press, Los Alamitos, CA, 70-75.
16. MARINISSEN, E. J., ZORIAN, Y., KAPUR, R., TAYLOR, T., AND WHETSEL, L. 1999. Towards a standard for embedded core test: An example. In Proceedings of the IEEE International Test Conference. IEEE Computer Society Press, Los Alamitos, CA, 616-627.
17. MARINISSEN, E. J., ARENDSEN, R., BOS, G., DINGEMANSE, H., LOUSBERG, M., AND WOUTERS, C. 1998. A structured and scalable mechanism for test access to embedded reusable cores. In Proceedings of the International Test Conference. IEEE Computer Society Press, Los Alamitos, CA, 284-293.
18. SUGIHARA, M., DATE, H., AND YASUURA, H. 1998. A novel test methodology for core-based system LSIs and a testing time minimization problem. In Proceedings of the International Test Conference. IEEE Computer Society Press, Los Alamitos, CA, 465-472.
19. WILLIAMS, H. P. 1985. Model Building in Mathematical Programming. 2nd ed. John Wiley, New York, NY.
20. VARMA, P. AND BHATIA, S. 1998. A structured test re-use methodology for core-based system chips. In Proceedings of the International Test Conference. IEEE Computer Society Press, Los Alamitos, CA, 294-302.
21. ZORIAN, Y., MARINISSEN, E. J., AND DEY, S. 1998. Testing embedded-core based system chips. In Proceedings of the International Test Conference. IEEE Computer Society Press, Los Alamitos, CA, 130-143.
22. ZORIAN, Y. 1997. Test requirements for embedded core-based systems and IEEE P1500. In Proceedings of the International Test Conference. IEEE Computer Society Press, Los Alamitos, CA, 191-199.