ILP formulation to optimize test access mechanism in system-on-chip testing

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 902-910

  Nourani, Mehrdad ^a   Papachristou, Christos ^a  

^a UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; INTEGER PROGRAMMING; INTEGRATED CIRCUIT TESTING; LINEAR PROGRAMMING; MICROCONTROLLERS;

BRIDGE ACCESS GRAPH; INTEGER LINEAR PROGRAMMING; SYSTEM ON CHIP TESTING; TEST ACCESS MECHANISM;

DESIGN FOR TESTABILITY;

EID: 0034483643     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)