메뉴 건너뛰기




Volumn , Issue , 2013, Pages

Approximate computing: An emerging paradigm for energy-efficient design

Author keywords

adder; approximate computing; low energy design; multiplier; probabilistic computing; stochastic computation

Indexed keywords

APPROXIMATE COMPUTING; LOW-ENERGY DESIGN; MULTIPLIER; PROBABILISTIC COMPUTING; STOCHASTIC COMPUTATIONS;

EID: 84883335440     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2013.6569370     Document Type: Conference Paper
Times cited : (931)

References (65)
  • 1
    • 84855774743 scopus 로고    scopus 로고
    • MACACO: Modeling and analysis of circuits for approximate computing
    • November
    • R. Venkatesan, A. Agarwal, K. Roy, and A. Raghunathan, MACACO: Modeling and analysis of circuits for approximate computing, in Proc. ICCAD, pp. 667-673, November 2011.
    • (2011) Proc. ICCAD , pp. 667-673
    • Venkatesan, R.1    Agarwal, A.2    Roy, K.3    Raghunathan, A.4
  • 7
    • 24344467032 scopus 로고    scopus 로고
    • Toward hardware-redundant, fault-tolerant logic for nanoelectronics
    • July/August
    • J. Han, J. Gao, Y. Qi, P. Jonker, J.A.B. Fortes. Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics, IEEE Design and Test of Computers, vol. 22, no. 4, pp. 328-339, July/August 2005.
    • (2005) IEEE Design and Test of Computers , vol.22 , Issue.4 , pp. 328-339
    • Han, J.1    Gao, J.2    Qi, Y.3    Jonker, P.4    Fortes, J.A.B.5
  • 8
    • 0035440487 scopus 로고    scopus 로고
    • Stochastic neural computation I: Computational elements
    • Sept
    • B. Brown and H. Card, Stochastic neural computation I: Computational elements, IEEE Trans. Computers, vol. 50, pp. 891-905, Sept. 2001.
    • (2001) IEEE Trans. Computers , vol.50 , pp. 891-905
    • Brown, B.1    Card, H.2
  • 11
    • 78649938802 scopus 로고    scopus 로고
    • An architecture for fault-tolerant computation with stochastic logic
    • Jan
    • W. Qian, X. Li, M.D. Riedel, K. Bazargan and D.J. Lilja, An architecture for fault-tolerant computation with stochastic logic, IEEE Trans. Computers, vol. 60, pp. 93-105, Jan. 2011.
    • (2011) IEEE Trans. Computers , vol.60 , pp. 93-105
    • Qian, W.1    Li, X.2    Riedel, M.D.3    Bazargan, K.4    Lilja, D.J.5
  • 12
    • 84872064308 scopus 로고    scopus 로고
    • A spectral transform approach to stochastic circuits
    • A. Alaghi and J.P. Hayes. A spectral transform approach to stochastic circuits, in Proc. ICCD, pp. 315-321, 2012.
    • (2012) Proc. ICCD , pp. 315-321
    • Alaghi, A.1    Hayes, J.P.2
  • 13
    • 84883393093 scopus 로고    scopus 로고
    • Logical computation on stochastic bit streams with linear finite state machines
    • press
    • P. Li, D. Lilja, W. Qian, M. Riedel and K. Bazargan, Logical computation on stochastic bit streams with linear finite state machines. IEEE Trans. Computers, in press.
    • IEEE Trans. Computers
    • Li, P.1    Lilja, D.2    Qian, W.3    Riedel, M.4    Bazargan, K.5
  • 14
    • 84883381062 scopus 로고    scopus 로고
    • A stochastic computational approach for accurate and efficient reliability evaluation
    • in press
    • J. Han, H. Chen, J. Liang, P. Zhu, Z. Yang and F. Lombardi, A stochastic computational approach for accurate and efficient reliability evaluation, IEEE Trans. Computers, in press.
    • IEEE Trans. Computers
    • Han, J.1    Chen, H.2    Liang, J.3    Zhu, P.4    Yang, Z.5    Lombardi, F.6
  • 15
    • 84874947485 scopus 로고    scopus 로고
    • A fast and accurate fault tree analysis based on stochastic logic implemented on field-programmable gate arrays
    • Mar
    • H. Aliee and H.R. Zarandi, A fast and accurate fault tree analysis based on stochastic logic implemented on field-programmable gate arrays, IEEE Trans. Reliability, vol. 62, pp. 13-22, Mar. 2013.
    • (2013) IEEE Trans. Reliability , vol.62 , pp. 13-22
    • Aliee, H.1    Zarandi, H.R.2
  • 18
    • 84859059850 scopus 로고    scopus 로고
    • ERSA: Error resilient system architecture for probabilistic applications
    • H. Cho, L. Leem, and S. Mitra, ERSA: Error resilient system architecture for probabilistic applications, IEEE Trans. CAD of Integrated Circuits and Systems, vol. 31, no. 4, pp. 546-558, 2012.
    • (2012) IEEE Trans. CAD of Integrated Circuits and Systems , vol.31 , Issue.4 , pp. 546-558
    • Cho, H.1    Leem, L.2    Mitra, S.3
  • 22
    • 84863550151 scopus 로고    scopus 로고
    • What to do about the end of Moore's law, probably!
    • K. Palem and A. Lingamneni, What to do about the end of Moore's law, probably! In Proc. DAC, pp. 924-929, 2012.
    • (2012) Proc. DAC , pp. 924-929
    • Palem, K.1    Lingamneni, A.2
  • 24
    • 77951023589 scopus 로고    scopus 로고
    • Bio-inspired imprecise computational blocks for efficient vlsi implementation of softcomputing applications
    • April
    • H.R. Mahdiani, A. Ahmadi, S.M. Fakhraie, C. Lucas, Bio-inspired imprecise computational blocks for efficient vlsi implementation of softcomputing applications, IEEE Trans. Circuits and Systems I: Regular Papers, vol. 57, no. 4, pp. 850-862, April 2010.
    • (2010) IEEE Trans. Circuits and Systems I: Regular Papers , vol.57 , Issue.4 , pp. 850-862
    • Mahdiani, H.R.1    Ahmadi, A.2    Fakhraie, S.M.3    Lucas, C.4
  • 25
    • 1842425446 scopus 로고    scopus 로고
    • Speeding up processing with approximation circuits
    • S.-L. Lu, Speeding up processing with approximation circuits, Computer, vol. 37, no. 3, pp. 67-73, 2004.
    • (2004) Computer , vol.37 , Issue.3 , pp. 67-73
    • Lu, S.-L.1
  • 26
    • 49749100727 scopus 로고    scopus 로고
    • Variable latency speculative addition: A new paradigm for arithmetic circuit design
    • A.K. Verma, P. Brisk and P. Ienne, Variable latency speculative addition: A new paradigm for arithmetic circuit design, in Proc. DATE, pp. 1250-1255, 2008.
    • (2008) Proc. DATE , pp. 1250-1255
    • Verma, A.K.1    Brisk, P.2    Ienne, P.3
  • 27
    • 77950428071 scopus 로고    scopus 로고
    • An enhanced low-power high-speed adder for error-tolerant application
    • N. Zhu, W.L. Goh and K.S. Yeo, An enhanced low-power high-speed adder for error-tolerant application, in Proc. ISIC'09, pp. 69-72, 2009.
    • (2009) Proc. ISIC'09 , pp. 69-72
    • Zhu, N.1    Goh, W.L.2    Yeo, K.S.3
  • 28
    • 77955174229 scopus 로고    scopus 로고
    • Design of lowpower high-speed truncation-error-tolerant adder and its application in digital signal processing
    • August
    • N. Zhu, W.L. Goh, W.Zhang, K.S. Yeo and Z.H. Kong, Design of lowpower high-speed truncation-error-tolerant adder and its application in digital signal processing, IEEE Trans. VLSI Systems, 18 (8): 1225-1229, August 2010.
    • (2010) IEEE Trans. VLSI Systems , vol.18 , Issue.8 , pp. 1225-1229
    • Zhu, N.1    Goh, W.L.2    Zhang, W.3    Yeo, K.S.4    Kong, Z.H.5
  • 29
    • 79851489663 scopus 로고    scopus 로고
    • Enhanced low-power highspeed adder for error-tolerant application
    • N. Zhu, W.L. Goh, G. Wang and K.S. Yeo, Enhanced low-power highspeed adder for error-tolerant application, in Proc. IEEE Intl. SoC Design Conf., pp. 323-327, 2010.
    • (2010) Proc. IEEE Intl. SoC Design Conf , pp. 323-327
    • Zhu, N.1    Goh, W.L.2    Wang, G.3    Yeo, K.S.4
  • 30
    • 84857417752 scopus 로고    scopus 로고
    • Ultra low-power high-speed flexible probabilistic adder for error-tolerant applications
    • N. Zhu, W.L. Goh and K.S. Yeo, Ultra low-power high-speed flexible probabilistic adder for error-tolerant applications, in Proc. Intl. SoC Design Conf., pp. 393-396, 2011.
    • (2011) Proc. Intl. SoC Design Conf , pp. 393-396
    • Zhu, N.1    Goh, W.L.2    Yeo, K.S.3
  • 31
    • 84862058742 scopus 로고    scopus 로고
    • High performance reliable variable latency carry select addition
    • K. Du, P. Varman and K. Mohanram, High performance reliable variable latency carry select addition, in Proc. DATE, pp. 1257-1262, 2012.
    • (2012) Proc. DATE , pp. 1257-1262
    • Du, K.1    Varman, P.2    Mohanram, K.3
  • 32
    • 84863554442 scopus 로고    scopus 로고
    • Accuracy-configurable adder for approximate arithmetic designs
    • A.B. Kahng and S. Kang, Accuracy-configurable adder for approximate arithmetic designs, in Proc. DAC, pp. 820-825, 2012.
    • (2012) Proc. DAC , pp. 820-825
    • Kahng, A.B.1    Kang, S.2
  • 33
    • 84872352510 scopus 로고    scopus 로고
    • Modeling and synthesis of quality-energy optimal approximate adders
    • J. Miao, K. He, A. Gerstlauer and M. Orshansky Modeling and synthesis of quality-energy optimal approximate adders, in Proc. ICCAD, pp. 728, 2012.
    • (2012) Proc. ICCAD , pp. 728
    • Miao, J.1    He, K.2    Gerstlauer, A.3    Orshansky, M.4
  • 34
    • 84863551520 scopus 로고    scopus 로고
    • A methodology for energy-quality tradeoff using imprecise hardware
    • J. Huang, J. Lach, and G. Robins, A methodology for energy-quality tradeoff using imprecise hardware, in Proc. DAC, pp. 504-509, 2012.
    • (2012) Proc. DAC , pp. 504-509
    • Huang, J.1    Lach, J.2    Robins, G.3
  • 36
    • 79952849170 scopus 로고    scopus 로고
    • Trading accuracy for power with an underdesigned multiplier architecture
    • January
    • P Kulkarni, P Gupta and M Ercegovac, Trading accuracy for power with an underdesigned multiplier architecture, in Proc. 24th Intl. Conf. on VLSI Design, pp. 346-351, January 2011.
    • (2011) Proc. 24th Intl. Conf. on VLSI Design , pp. 346-351
    • Kulkarni, P.1    Gupta, P.2    Ercegovac, M.3
  • 38
    • 49749120584 scopus 로고    scopus 로고
    • Approximate logic circuits for low overhead, non-intrusive concurrent error detection
    • M.R. Choudhury and Kartik Mohanram, Approximate logic circuits for low overhead, non-intrusive concurrent error detection, in Proc. DATE, pp. 903-908, 2008.
    • (2008) Proc. DATE , pp. 903-908
    • Choudhury, M.R.1    Mohanram, K.2
  • 39
    • 77953116665 scopus 로고    scopus 로고
    • Approximate logic synthesis for error tolerant applications
    • D. Shin and S.K. Gupta, Approximate logic synthesis for error tolerant applications, in Proc. DATE, pp. 957-960, 2010.
    • (2010) Proc. DATE , pp. 957-960
    • Shin, D.1    Gupta, S.K.2
  • 40
    • 84883366732 scopus 로고    scopus 로고
    • A new circuit simplification method for error tolerant applications
    • D. Shin and S.K. Gupta, A new circuit simplification method for error tolerant applications, in Proc. DATE, pp. 1-6, 2011.
    • (2011) Proc. DATE , pp. 1-6
    • Shin, D.1    Gupta, S.K.2
  • 42
    • 13244282954 scopus 로고    scopus 로고
    • Intelligible test techniques to support error-tolerance
    • M.A. Breuer, Intelligible test techniques to support error-tolerance, in Proc. IEEE Asian Test Symposium, pp. 386-393, 2004.
    • (2004) Proc. IEEE Asian Test Symposium , pp. 386-393
    • Breuer, M.A.1
  • 44
    • 84883398292 scopus 로고    scopus 로고
    • New metrics for the reliability of approximate and probabilistic adders
    • in press
    • J. Liang, J. Han, F. Lombardi, New metrics for the reliability of approximate and probabilistic adders, IEEE Trans. Computers, in press.
    • IEEE Trans. Computers
    • Liang, J.1    Han, J.2    Lombardi, F.3
  • 45
    • 79952964437 scopus 로고    scopus 로고
    • Exploring the fidelity-efficiency design space using imprecise arithmetic
    • J. Huang and J. Lach, Exploring the fidelity-efficiency design space using imprecise arithmetic, in Proc. ASPDAC, pp. 579-584, 2011.
    • (2011) Proc. ASPDAC , pp. 579-584
    • Huang, J.1    Lach, J.2
  • 46
    • 77953116122 scopus 로고    scopus 로고
    • A general mathematical model of probabilistic ripple-carry adders
    • M.S.K. Lau, K.V. Ling, Y.C. Chu and A. Bhanu, A general mathematical model of probabilistic ripple-carry adders, in Proc. DATE, pp. 1100-1105, 2010.
    • (2010) Proc. DATE , pp. 1100-1105
    • Lau, M.S.K.1    Ling, K.V.2    Chu, Y.C.3    Bhanu, A.4
  • 53
    • 0032202808 scopus 로고    scopus 로고
    • An energy/security scalable encryption processor using an embedded variable voltage DC/DC converter
    • J. Goodman, A. Dancy, and A.P. Chandrakasan, An energy/security scalable encryption processor using an embedded variable voltage DC/DC converter, IEEE Journal of Solid-State Circuits, 33(11):1799-1809, 1998.
    • (1998) IEEE Journal of Solid-State Circuits , vol.33 , Issue.11 , pp. 1799-1809
    • Goodman, J.1    Dancy, A.2    Chandrakasan, A.P.3
  • 54
    • 85009395461 scopus 로고    scopus 로고
    • Energy efficient filtering using adaptive precision and variable voltage
    • A. Sinha and A.P. Chandrakasan, Energy efficient filtering using adaptive precision and variable voltage, IEEE Intl. ASIC/SOC Conference, pp. 327-331, 1999.
    • (1999) IEEE Intl. ASIC/SOC Conference , pp. 327-331
    • Sinha, A.1    Chandrakasan, A.P.2
  • 55
    • 77956193467 scopus 로고    scopus 로고
    • Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency
    • V. Chippa, D. Mohapatra, A. Raghunathan, K. Roy, and S. Chakradhar, Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency, In Proc. DAC, pp. 555-560, 2010.
    • (2010) Proc. DAC , pp. 555-560
    • Chippa, V.1    Mohapatra, D.2    Raghunathan, A.3    Roy, K.4    Chakradhar, S.5
  • 56
    • 77951877211 scopus 로고    scopus 로고
    • Dynamic bit-width adaptation in DCT: An approach to trade off image quality and computation energy
    • May
    • J. Park, J. Choi, and K. Roy, Dynamic bit-width adaptation in DCT: an approach to trade off image quality and computation energy, IEEE Trans. VLSI Systems, vol. 18, no. 5, pp. 787-793, May 2011.
    • (2011) IEEE Trans. VLSI Systems , vol.18 , Issue.5 , pp. 787-793
    • Park, J.1    Choi, J.2    Roy, K.3
  • 58
    • 33746638860 scopus 로고    scopus 로고
    • Energy-efficient soft error-tolerant digital signal processing
    • B. Shim and N.R. Shanbhag, Energy-efficient soft error-tolerant digital signal processing, IEEE Trans. VLSI Systems, 14(4):336-348, 2006.
    • (2006) IEEE Trans. VLSI Systems , vol.14 , Issue.4 , pp. 336-348
    • Shim, B.1    Shanbhag, N.R.2
  • 59
    • 2542436055 scopus 로고    scopus 로고
    • Reliable low-power digital signal processing via reduced precision redundancy
    • B. Shim, S. Sridhara, and N. Shanbhag, Reliable low-power digital signal processing via reduced precision redundancy, IEEE Trans. VLSI Systems (TVLSI), 12(5): 497-510, 2004.
    • (2004) IEEE Trans. VLSI Systems (TVLSI) , vol.12 , Issue.5 , pp. 497-510
    • Shim, B.1    Sridhara, S.2    Shanbhag, N.3
  • 61
    • 84855796123 scopus 로고    scopus 로고
    • Design of voltage-scalable meta-functions for approximate computing
    • D. Mohapatra, V.K. Chippa, A. Raghunathan, and K. Roy, Design of voltage-scalable meta-functions for approximate computing, Proc. DATE, pp.1-6, 2011.
    • (2011) Proc. DATE , pp. 1-6
    • Mohapatra, D.1    Chippa, V.K.2    Raghunathan, A.3    Roy, K.4
  • 63
    • 84883366885 scopus 로고    scopus 로고
    • Controlled timing-error acceptance for low energy IDCT design
    • K. He, A. Gerstlauer, and M. Orshansky, Controlled timing-error acceptance for low energy IDCT design, in Proc. DATE, pp. 1-6, 2011.
    • (2011) Proc. DATE , pp. 1-6
    • He, K.1    Gerstlauer, A.2    Orshansky, M.3
  • 64
    • 74749108011 scopus 로고    scopus 로고
    • System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning
    • G. Karakonstantis, D. Mohapatra, K. Roy, System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning, IEEE Workshop on Signal Processing Systems (SIPS), pp. 133-138, 2009.
    • (2009) IEEE Workshop on Signal Processing Systems SIPS , pp. 133-138
    • Karakonstantis, G.1    Mohapatra, D.2    Roy, K.3
  • 65
    • 34548316191 scopus 로고    scopus 로고
    • Process variation tolerant low power DCT architecture
    • N. Banerjee, G. Karakonstantis, and K. Roy, Process variation tolerant low power DCT architecture, in Proc. DATE, pp. 630-635, 2007.
    • (2007) Proc. DATE , pp. 630-635
    • Banerjee, N.1    Karakonstantis, G.2    Roy, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.