An enhanced low-power high-speed adder for error-tolerant application

ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings

Volumn , Issue , 2009, Pages 69-72

  Zhu, Ning ^a   Goh, Wang Ling ^a   Yeo, Kiat Seng ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Adders; Error tolerance; High speed integrated circuits; Low power design

Indexed keywords

ERROR TOLERANT; HIGH-SPEED ADDERS; HIGH-SPEED INTEGRATED CIRCUITS; LOW POWER; LOW-POWER DESIGN; POWER CONSUMPTION; POWER-DELAY PRODUCTS; SPEED PERFORMANCE; TYPE II; VLSI DESIGN; VLSI TECHNOLOGY;

ADDERS; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; ERRORS; INTEGRATED CIRCUITS;

SPEED;

EID: 77950428071     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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