메뉴 건너뛰기




Volumn , Issue , 2012, Pages 728-735

Modeling and synthesis of quality-energy optimal approximate adders

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; COMPUTATION THEORY; COMPUTER CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; ENERGY CONSERVATION; ERRORS; IMAGE PROCESSING; LOGIC SYNTHESIS; PARETO PRINCIPLE; SIGNAL TO NOISE RATIO;

EID: 84872352510     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2429384.2429542     Document Type: Conference Paper
Times cited : (109)

References (15)
  • 2
    • 0035706021 scopus 로고    scopus 로고
    • Soft digital signal processing
    • R. Hedge and N. R. Shanbhag. Soft digital signal processing. TVLSI, 9(6), 2000.
    • (2000) TVLSI , vol.9 , pp. 6
    • Hedge, R.1    Shanbhag, N.R.2
  • 3
    • 80052754056 scopus 로고    scopus 로고
    • An approach to energy-error tradeoffs in approximate ripple carry adders
    • Z. Kedem, V. Mooney, K. Muntimadugu, and K. Palem. An approach to energy-error tradeoffs in approximate ripple carry adders. In ISLPED, 2011.
    • (2011) ISLPED
    • Kedem, Z.1    Mooney, V.2    Muntimadugu, K.3    Palem, K.4
  • 4
    • 84872303910 scopus 로고    scopus 로고
    • Arithmetic data value speculation
    • D. R. Kelly and B. J. Phillips. Arithmetic data value speculation. In ACSAC, 2005.
    • (2005) ACSAC
    • Kelly, D.R.1    Phillips, B.J.2
  • 5
    • 77951880041 scopus 로고    scopus 로고
    • Low-power multimedia system design by aggressive voltage scaling
    • F. Kurdahi, A. Eltawil, K. Yi, S. Cheng, and A. Khajeh. Low-power multimedia system design by aggressive voltage scaling. TVLSI, 18(5), 2010.
    • TVLSI , vol.18 , Issue.5 , pp. 2010
    • Kurdahi, F.1    Eltawil, A.2    Yi, K.3    Cheng, S.4    Khajeh, A.5
  • 6
    • 79957559242 scopus 로고    scopus 로고
    • Energy parsimonious circuit design through probabilistic pruning
    • A. Lingamneni, C. Enz, J.-L. Nagel, K. Palem, and C. Piguet. Energy parsimonious circuit design through probabilistic pruning. In DATE, 2011
    • (2011) DATE
    • Lingamneni, A.1    Enz, C.2    Nagel, J.-L.3    Palem, K.4    Piguet, C.5
  • 7
    • 1842425446 scopus 로고    scopus 로고
    • Speeding up processing with approximation circuits
    • S.-L. Lu. Speeding up processing with approximation circuits. Computer, 37(3), 2004.
    • (2004) Computer , vol.37 , Issue.3
    • Lu, S.-L.1
  • 8
    • 0027277648 scopus 로고
    • Espresso-signature: A new exact minimizer for logic functions
    • P. McGeer, J. Sanghavi, R. Brayton, and A. Vincentelli. Espresso-signature: A new exact minimizer for logic functions. In DAC, 1993.
    • (1993) DAC
    • McGeer, P.1    Sanghavi, J.2    Brayton, R.3    Vincentelli, A.4
  • 10
    • 85009395461 scopus 로고    scopus 로고
    • Energy efficient filtering using adaptive precision and variable voltage
    • A. Sinha and A. P. Chandrakasan. Energy efficient filtering using adaptive precision and variable voltage. ASIC SOC Conference, 1999.
    • (1999) ASIC SOC Conference
    • Sinha, A.1    Chandrakasan, A.P.2
  • 11
    • 49749100727 scopus 로고    scopus 로고
    • Variable latency speculative addition: A new paradigm for arithmetic circuit design
    • A. K. Verma, P. Brisk, and P. Ienne. Variable latency speculative addition: a new paradigm for arithmetic circuit design. In DATE, 2008.
    • (2008) DATE
    • Verma, A.K.1    Brisk, P.2    Ienne, P.3
  • 13
    • 0000194406 scopus 로고    scopus 로고
    • A low-power dct core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization
    • T. Xanthopoulos and A. Chandrakasan. A low-power dct core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization. J. Solid-State Circuits, 35(5), 2000.
    • (2000) J. Solid-State Circuits , vol.35 , Issue.5
    • Xanthopoulos, T.1    Chandrakasan, A.2
  • 14
    • 79851489663 scopus 로고    scopus 로고
    • Enhanced low-power high-speed adder for error-tolerant application
    • N. Zhu, W. L. Goh, G. Wang, and K. S. Yeo. Enhanced low-power high-speed adder for error-tolerant application. In ISOCC, 2010.
    • (2010) ISOCC
    • Zhu, N.1    Goh, W.L.2    Wang, G.3    Yeo, K.S.4
  • 15
    • 77955174229 scopus 로고    scopus 로고
    • Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
    • N. Zhu, W. L. Goh, W. Zhang, K. S. Yeo, and Z. H. Kong. Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. TVLSI, 18(8), 2010.
    • (2010) TVLSI , vol.18 , Issue.8
    • Zhu, N.1    Goh, W.L.2    Zhang, W.3    Yeo, K.S.4    Kong, Z.H.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.