Dynamic bit-width adaptation in DCT: An approach to trade off image quality and computation energy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 5, 2010, Pages 787-793

  Park, J ^a   Choi, Jung Hwan ^b   Roy, Kaushik ^c  

^a Korea University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c PURDUE UNIVERSITY   (United States)

Author keywords

Discrete cosine transform (DCT); Dynamic bit width; Low power design; Reconfigurable architecture

Indexed keywords

ADAPTATION SCHEME; BIT-WIDTH; CARRY SAVE ADDER; COMPUTATION ENERGY; DCT ALGORITHMS; DCT COEFFICIENTS; DIFFERENT FREQUENCY; LOW-POWER DESIGN; NORMAL OPERATIONS; POWER CONSUMPTION; POWER SAVINGS; RE-CONFIGURABLE; RECONFIGURABLE ARCHITECTURE; SELECTION ALGORITHM; SENSITIVITY DIFFERENCE; TRADE OFF;

COSINE TRANSFORMS; DEGRADATION; ELECTRIC POWER SUPPLIES TO APPARATUS; IMAGE QUALITY; TREES (MATHEMATICS);

DISCRETE COSINE TRANSFORMS;

EID: 77951877211     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2016839     Document Type: Article

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