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Volumn , Issue , 2011, Pages 579-584

Exploring the fidelity-efficiency design space using imprecise arithmetic

Author keywords

[No Author keywords available]

Indexed keywords

ADDER DESIGN; CIRCUIT COMPONENTS; CIRCUIT DESIGN TECHNIQUES; CORDIC ALGORITHMS; DESIGN SPACE EXPLORATION; DESIGN SPACES; ENERGY BENEFITS; ERROR CHARACTERISTICS; ERROR TOLERANT; GENERAL METHODOLOGIES;

EID: 79952964437     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722256     Document Type: Conference Paper
Times cited : (28)

References (16)
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  • 3
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  • 4
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    • Variable latency speculative addition: A new paradigm for arithmetic circuit design
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  • 7
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    • A low-power multiplication algorithm for signal processing in wireless sensor networks
    • A. Abdelgawad, S. Abdelhak, S. Ghosh, M. Bayoumi, "A low-power multiplication algorithm for signal processing in wireless sensor networks," IMSCAS, 695-698, 2009.
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  • 8
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  • 9
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    • J. Bau, R. Hankins, Q. Jacobson, S. Mitra, B. Saha, A. Adl-Tabatabai, "Error resilient system architecture (ERSA) for probabilistic applications," DATE, 1560-1565, 2010.
    • (2010) DATE , pp. 1560-1565
    • Bau, J.1    Hankins, R.2    Jacobson, Q.3    Mitra, S.4    Saha, B.5    Adl-Tabatabai, A.6
  • 10
    • 15044339297 scopus 로고    scopus 로고
    • Razor: Circuit-level correction of timing errors for low-power operation
    • Nov.
    • D. Ernst, et al. "Razor: Circuit-level correction of timing errors for low-power operation," IEEE Micro, 24(6):10-20, Nov. 2004.
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  • 12
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    • Multi-dimensional circuit and micro-architecture level optimization
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.