Toward hardware-redundant, fault-tolerant logic for nanoelectronics

IEEE Design and Test of Computers

Volumn 22, Issue 4, 2005, Pages 328-339

  Han, Jie ^a   Gao, Jianbo ^a   Qi, Yan ^b   Jonker, Pieter ^c   Fortes, José A B ^a  

^a J Crayton Pruitt Family Department of Biomedical Engineering   (United States)

^b JOHNS HOPKINS UNIVERSITY   (United States)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BIFURCATION (MATHEMATICS); COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC GATES; MARKOV PROCESSES; MATHEMATICAL MODELS; MULTIPLEXING; RELIABILITY;

FAULT TOLERANT LOGIC; MARKOV CHAIN MODELS; NANOELECTRONICS;

NANOTECHNOLOGY;

EID: 24344467032     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2005.97     Document Type: Review

References (12)

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11. J.B. Gao, Y. Qi, and J.A.B. Fortes, "Bifurcations and Fundamental Error Bounds for Fault-Tolerant Computations," to appear in IEEE Trans. Nanotechnology.
12. J. Han and P. Jonker, "From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers," Proc. 17th Int'l Conf. Pattern Recognition (ICPR 04), IEEE CS Press, 2004, pp. 2-7.