Variable latency speculative addition: a new paradigm for arithmetic circuit design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 1250-1255

  Verma, Ajay K ^a   Brisk, Philip ^a   Ienne, Paolo ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL THEORY; DELAY CIRCUITS; DIGITAL ARITHMETIC; ELECTRIC NETWORK ANALYSIS; ERROR CORRECTION; INDUSTRIAL ENGINEERING; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATING CIRCUITS; LOGIC CIRCUITS; NETWORKS (CIRCUITS); PROBABILITY; TESTING;

ADDER DESIGNS; ARITHMETIC CIRCUITS; HIGH PROBABILITY; KEY COMPONENTS; LOW PROBABILITY; LOWER BOUNDS;

ADDERS;

EID: 49749100727     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484850     Document Type: Conference Paper

References (13)

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