System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2009, Pages 133-138

  Karakonstantis, Georgios ^a   Mohapatra, Debabrata ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Error resilient; Low power; Supply voltage scaling

Indexed keywords

ADAPTIVE QUALITY; CHANNEL NOISE; DESIGN METHODOLOGY; ERROR RESILIENCY; ERROR-RESILIENT; LARGE POWER; LOW POWER SUPPLY VOLTAGE; OPERATING CONDITION; OUTPUT QUALITY; PROCESS VARIATION; QUALITY DEGRADATION; SYSTEM LEVEL DESIGN; SYSTEM LEVELS; SYSTEM-LEVEL INTERACTIONS; UNEQUAL ERROR PROTECTIONS; VOLTAGE OVERSCALING;

IMAGE QUALITY;

SIGNAL PROCESSING;

EID: 74749108011     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2009.5336238     Document Type: Conference Paper

References (12)

1. J. Rabaey et al., "Digital Integated Circuits", Prentice Hall, 2002
2. S.Borkar et al., "Parameter variations and impact on circuits and microarchitecture", IEEE DAC, 2003.
3. N. Banerjee et al., "Low Power Variation Tolerant DCT Architecture, IEEE DATE, 2007.
4. J.-S. Chiang et. al.,"A High Throughput 2-Dimensional DCT/IDCT Architecture for real-time image and video system", IEEE ICECS, 2001.
5. T. Xanthopoulos , et.al, "Low-Power IDCT Macrocell for MPEG-2 MP@ML Exploiting Data Distribution Properties for Minimal Activity", IEEE JSSC, 1999.
6. K. Lengwehasatit, et. al, "DCT computation based on variable complexity fast approximations", IEEE ICIP, 1998.
7. V.Bhaskaran et al., "Image and Video Compression Standard Algorithms and Architecture", Kluwer Academic Publishers, 1996.
8. http://r0k.us/graphics/kodak/
9. C.H. Kim et al., "On-die CMOS leakage current sensor for measuring process variation in sub-90nm generations", Symp . of VLSI Circuits, 2004.
10. ARMLIBS 90nm, http://www.arm.com/
11. S. Kulkarni, et. al, "New level converters and level converting logic circuits for multi-VDD low power design", IEEE System-on-Chip, 2003.
12. S.C. Hsia, et. al, "VLSI Implementation of High-Performance Error Concealment Processor for TV Broadcasting",IEEE Trans. on CSVT,2007.