Low-power high-speed multiplier for error-tolerant application

2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

Volumn , Issue , 2010, Pages

  Kyaw, Khaing Yin ^a   Goh, Wang Ling ^a   Yeo, Kiat Seng ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

CMOS technology; Error tolerant; High speed integrated circuits; Low power; Multiplier; Truncated

Indexed keywords

CMOS TECHNOLOGY; ERROR-TOLERANT; HIGH SPEED INTEGRATED CIRCUITS; LOW POWER; MULTIPLIER; TRUNCATED;

DESIGN; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUITS; MULTIPLYING CIRCUITS; SOLID STATE DEVICES;

CMOS INTEGRATED CIRCUITS;

EID: 79952520077     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2010.5713751     Document Type: Conference Paper

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