Ultra low-power high-speed flexible probabilistic adder for error-tolerant applications

2011 International SoC Design Conference, ISOCC 2011

Volumn , Issue , 2011, Pages 393-396

  Zhu, Ning ^a   Goh, Wang Ling ^a   Yeo, Kiat Seng ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Adders; Error rate; Error tolerance (ET); High speed integrated circuits; Low power design

Indexed keywords

ADDERS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC POWER UTILIZATION; ERRORS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; SPEED; VLSI CIRCUITS;

CIRCUIT DESIGNS; ERROR RATE; ERROR TOLERANCE; HIGH-SPEED INTEGRATED CIRCUITS; LOW-POWER DESIGN; SPEED PERFORMANCE; ULTRA LOW POWER; VLSI TECHNOLOGY;

LOW POWER ELECTRONICS;

EID: 84857417752     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isocc.2011.6138614     Document Type: Conference Paper

References (10)

1. Zhu Ning, Zhang Weijia, Goh Wang Ling, Yeo Kiat Seng, and Kong Zhi Hui, "Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing", IEEE Transactions on Very Large Scale Integration (VLSI,) Systems, Vol. 18, Issue 8, pp. 1225-1229, Aug. 2010.
2. Melvin A. Breuer, "Let's think analog," in Proc. of the IEEE Computer Society Annual Symposium on VLSI, pp. 2-5, 2005.
3. M. A. Breuer and H. Zhu, "An Illustrated Methodology for Analysis of Error Tolerance," IEEE Design and Test Magazine, pp. 168-177, 2008.
4. H. Kakavand and A. El Gamal, "On Energy-Reliability Tradeoff in analog-to-Digital Converters with Imperfect Comparators," Proc. 40th Ann. Conf. Information Sciences and Systems (CISS 06), pp. 1366-1371; http://www288.pair.com/ciss/ciss/numbered/297.pdf.
5. I.S. Chong and A. Ortega, "Hardware Testing for Error Tolerant Multimedia Compression Based on Linear Transforms," Proc. 20th IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFT 05), IEEE CS Press, pp. 523-534, 2005.
6. th IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFT 05), IEEE CS Press, pp. 514-522, 2005.
7. N. Zhu, W. L. Goh, and K. S. Yeo, "An Enhanced Low-Power High-Speed Adder For Error-Tolerant Application", Int'l Sym. Integrated Circuits (ISIC 2009), pp. 69-72, Sep. 2009.
8. Wallace, W.F, Dlay, S.S, Hinton, O.R, "Probabilistic carry state estimate for improved asynchronous adder performance", Computers and Digital Techniques, IEE proceedings, page 221-226, 2001.
9. N. R. Shanbhag, "Reliable and efficient system-on-chip design," IEEE Computer, 37(3): pp. 42-50, May 2004.
10. M. Lehman and N. Burla, "Skip techniques for high-speed carry propagation in binary arithmetic units," IRE Transactions on Electronic Computers, vol.EC-10, pp. 691-698, Dec. 1962.