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Volumn , Issue , 2012, Pages 315-321

A spectral transform approach to stochastic circuits

Author keywords

Design methodology; logic synthesis; probabilistic methods; stochastic computing

Indexed keywords

A-TRANSFORM; ANALYSIS AND SYNTHESIS; AREA COST; ARITHMETIC FUNCTIONS; COMPREHENSIVE DESIGNS; COMPUTATIONAL ELEMENTS; DESIGN METHODOLOGY; DESIGN PROBLEMS; LOGIC SYNTHESIS; PROBABILISTIC METHODS; PSEUDO RANDOM; SC CIRCUITS; SOFT-ERROR TOLERANCE; SPECTRAL TRANSFORM; STOCHASTIC CIRCUITS; STOCHASTIC COMPUTING; TECHNOLOGY DEVELOPMENT;

EID: 84872064308     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2012.6378658     Document Type: Conference Paper
Times cited : (41)

References (16)
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    • (2011) Proc. Conf. Computer Design , pp. 154-161
    • Li, P.1    Lilja, D.J.2
  • 10
    • 84859989188 scopus 로고    scopus 로고
    • The synthesis of linear finite state machine-based stochastic computational elements
    • Li, P., Qian, W., Riedel, M.D., Bazargan, K., Lilja, D.J., "The synthesis of linear finite state machine-based stochastic computational elements," Proc. ASP-DAC., pp.757-762, 2012.
    • (2012) Proc. ASP-DAC. , pp. 757-762
    • Li, P.1    Qian, W.2    Riedel, M.D.3    Bazargan, K.4    Lilja, D.J.5
  • 12
    • 57149087094 scopus 로고    scopus 로고
    • Some topics in the analysis of Boolean functions
    • O'Donnell, R., "Some topics in the analysis of Boolean functions," Proc. ACM STOC Conf., pp.569-578, 2008.
    • (2008) Proc. ACM STOC Conf. , pp. 569-578
    • O'Donnell, R.1
  • 15
    • 78649938802 scopus 로고    scopus 로고
    • An architecture for fault-tolerant computation with stochastic logic
    • Qian, W., LI, X., Riedel, M.D., Bazargan, K., Lilja, D.J., "An architecture for fault-tolerant computation with stochastic logic," IEEE Trans. Computers, vol.60, pp.93-105, 2011.
    • (2011) IEEE Trans. Computers , vol.60 , pp. 93-105
    • Qian, W.1    Li, X.2    Riedel, M.D.3    Bazargan, K.4    Lilja, D.J.5
  • 16
    • 0003934798 scopus 로고
    • Univ. of California, Berkeley, Tech. Report UCB/ERL M92/41, Electronics Research Lab
    • Sentovich, E.M., et al., "SIS: A System for sequential circuit synthesis," Univ. of California, Berkeley, Tech. Report UCB/ERL M92/41, Electronics Research Lab, 1992.
    • (1992) SIS: A System for Sequential Circuit Synthesis
    • Sentovich, E.M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.