Inexact computing for ultra low-power nanometer digital circuit design

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Volumn , Issue , 2011, Pages 24-31

  Kim, Jaeyoon ^a   Tiwari, Sandip ^a  

^a Cornell University   (United States)

Author keywords

Energy Efficiency; MSB LSB weighted supply voltage scaling; Probability of Error; Reliability; Statistical performance metric; Variations

Indexed keywords

ADVANCED TECHNOLOGY; CALCULATION ERROR; CIRCUIT NOISE; CMOS LOGIC; COMPUTATIONAL ERROR; COMPUTATIONAL TASK; DIGITAL CIRCUIT DESIGN; HIGH-FREQUENCY PROPERTIES; LOW POWER; MSB-LSB WEIGHTED SUPPLY VOLTAGE SCALING; NANOMETER CIRCUITS; NOISE SOURCE; PROBABILITY OF ERROR; PROBABILITY OF ERRORS; SIMULATION RESULT; SOI CMOS; STATISTICAL FLUCTUATIONS; STATISTICAL PERFORMANCE; SUB-50 NM; TECHNOLOGY NODES; TOTAL POWER; TRANSFER CHARACTERISTICS; VARIATIONS;

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; DESIGN; ELECTRIC NETWORK TOPOLOGY; ENERGY EFFICIENCY; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; PROBABILISTIC LOGICS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 79961204319     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2011.5941479     Document Type: Conference Paper

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