Low-power digital signal processing using approximate adders

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 32, Issue 1, 2013, Pages 124-137

  Gupta, Vaibhav ^a   Mohapatra, Debabrata ^b   Raghunathan, Anand ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Approximate computing; low power; mirror adder

Indexed keywords

ALTERNATIVE APPROACH; APPROXIMATE COMPUTING; ARITHMETIC UNIT; CRITICAL PATHS; DESIGN ARCHITECTURE; ERROR RESILIENCY; FULL ADDERS; HUMAN BEING; IMAGE COMPRESSION ALGORITHMS; LOGIC COMPLEXITY; LOW POWER; MULTI-BITS; MULTIMEDIA APPLICATIONS; MULTIMEDIA DEVICE; NUMERICAL ACCURACY; NUMERICAL OUTPUT; POWER SAVINGS; QUALITY CONSTRAINTS; REDUCED COMPLEXITY; SIGNAL PROCESSING ALGORITHMS; TRANSISTOR LEVEL; VOLTAGE OVERSCALING; VOLTAGE-SCALING;

ALGORITHMS; DIGITAL SIGNAL PROCESSING; DISCRETE COSINE TRANSFORMS; FIR FILTERS; IMAGE COMPRESSION; MATHEMATICAL MODELS;

ADDERS;

EID: 84871997982     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2012.2217962     Document Type: Article

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