A fast and accurate fault tree analysis based on stochastic logic implemented on field-programmable gate arrays

IEEE Transactions on Reliability

Volumn 62, Issue 1, 2013, Pages 13-22

  Aliee, Hananeh ^a   Zarandi, Hamid Reza ^a  

^a AMIRKABIR UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

Fault tree analysis; field programmable gate array; single event upset; static and dynamic gates; stochastic logic

Indexed keywords

ANALYTICAL APPROACH; ARITHMETIC LOGIC; FAST CONVERGENCE; HARDWARE IMPLEMENTATIONS; SINGLE EVENT UPSETS; STATIC AND DYNAMIC; STOCHASTIC LOGIC; SYSTEM RELIABILITY MODELING;

COMPUTER CONTROL SYSTEMS; FAULT TREE ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GATES (TRANSISTOR); HARDWARE; MONTE CARLO METHODS; RELIABILITY ANALYSIS;

STOCHASTIC SYSTEMS;

EID: 84874947485     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2012.2221012     Document Type: Article

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