Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 8, 2010, Pages 1225-1229

  Zhu, Ning ^a   Goh, Wang Ling ^a   Zhang, Weija ^a   Yeo, Kiat Seng ^a   Kong, Zhi Hui ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Adders; digital signal processing (DSP); error tolerance; high speed integrated circuits; low power design; VLSI

Indexed keywords

DIGITAL SIGNAL PROCESSING SYSTEMS; ERROR TOLERANCE; ERROR TOLERANT; HIGH-SPEED; HIGH-SPEED INTEGRATED CIRCUITS; LOW POWER; LOW-POWER DESIGN; POTENTIAL APPLICATIONS; POWER CONSUMPTION; POWER-DELAY PRODUCTS; SPEED PERFORMANCE; VLSI DESIGN; VLSI TECHNOLOGY;

ADDERS; DESIGN; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSORS; ERRORS; INTEGRATED CIRCUITS; SIGNAL PROCESSING; SPEED; VLSI CIRCUITS;

DIGITAL SIGNAL PROCESSING;

EID: 77955174229     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2020591     Document Type: Article

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