SALSA: Systematic logic synthesis of approximate circuits

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 796-801

  Venkataramani, Swagath ^a   Sabne, Amit ^a   Kozhikkottu, Vivek ^a   Roy, Kaushik ^a   Raghunathan, Anand ^a  

^a Purdue University   (United States)

Author keywords

approximate computing; error resilience; logic synthesis; low power design; synthesis

Indexed keywords

APPLICATION DOMAINS; APPROXIMATE COMPUTING; BUILDING BLOCKES; CORRECT-BY-CONSTRUCTION; DATA-PATHS; DESIGN AUTOMATIONS; DESIGN COMPILER; ERROR CONSTRAINTS; ERROR RESILIENCE; EUCLIDEAN DISTANCE; HARDWARE IMPLEMENTATIONS; INHERENT ERRORS; LOGIC FUNCTIONS; LOGIC SYNTHESIS; LOGIC SYNTHESIS TOOLS; LOW-POWER DESIGN; MANUAL DESIGN; NEW DESIGN; OPTIMIZATION TECHNIQUES; Q-FUNCTIONS; QUALITY CONSTRAINTS; SYNOPSYS; SYNTHESIS TOOL; SYSTEMATIC METHODOLOGY;

COMPUTER AIDED DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; HARDWARE; SPECIFICATIONS; SYNTHESIS (CHEMICAL);

EQUIVALENT CIRCUITS;

EID: 84863541914     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228504     Document Type: Conference Paper

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