ERSA: Error resilient system architecture for probabilistic applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 4, 2012, Pages 546-558

  Cho, Hyungmin ^a   Leem, Larkhoon ^b   Mitra, Subhasish ^a  

^a Stanford University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Error resilience; hardware errors; probabilistic applications; reliability; robust systems

Indexed keywords

BAYESIAN NETWORK INFERENCE; BIT-ERRORS; COMPUTING SYSTEM; CONFIGURABLE; CONTROL-FLOW ERRORS; ENERGY EFFICIENT; ERROR INJECTION; ERROR PRONES; ERROR RATE; ERROR RESILIENCE; ERROR-RESILIENT; EXECUTION TIME; HARDWARE ERRORS; HARDWARE PROTOTYPE; HIGH RATE; HIGH-ORDER; INHERENT ERRORS; INTELLIGENT SOFTWARE; K-MEANS CLUSTERING; KILLER-APPLICATION; LOW COSTS; MANY-CORE ARCHITECTURE; MULTI CORE; OUTPUT QUALITY; REDUNDANCY TECHNIQUES; ROBUST SYSTEMS; STATIC MEMORY;

BIT ERROR RATE; RELIABILITY; SOFTWARE RELIABILITY; STATIC RANDOM ACCESS STORAGE;

ERRORS;

EID: 84859059850     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2179038     Document Type: Article

References (56)

1. M. Agostinelli, J. Hicks, J. Xu, B. Woolery, K. Mistry, K. Zhang, S. Jacobs, J. Jopling, W. Yang, B. Lee, T. Raz, M. Mehalel, P. Kolar, Y. Wang, J. Sandford, D. Pivin, C. Peterson, M. DiBattista, S. Pae, M. Jones, S. Johnson, and G. Subramanian, "Erratic fluctuations of SRAM cache Vmin at the 90 nm process technology node," in Proc. IEEE Int. EDM IEDM Tech. Dig., Dec. 2005, pp. 655-658. (Pubitemid 46370936)
2. S. Borkar, T. Karnik, and V. De, "Design and reliability challenges in nanometer technologies," in Proc. 41st Des. Autom. Conf., 2004, p. 75.
3. B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, "Digital circuit design challenges and opportunities in the era of nanoscale CMOS," Proc. IEEE, vol. 96, no. 2, pp. 343-365, Feb. 2008.
4. B. Li, L.-S. Peh, and P. Patra, "Impact of process and temperature variations on network-on-chip design exploration," in Proc. 2nd ACM/IEEE Int. Symp. NoCS, Apr. 2008, pp. 117-126. (Pubitemid 351715036)
5. P. Gelsinger. (2006, Jun.). Into the core . presented at Stanford Comput. Syst. Colloquium [Online]. Available: http://www.stanford.edu/class/ee380/ Abstracts/060607-EE380-Gelsinger.pdf
6. K. Bowman, J. Tschanz, S. Lu, P. Aseron, M. Khellah, A. Raychowdhury, B. Geuskens, C. Tokunaga, C. Wilkerson, T. Karnik, and V. De, "A 45 nm resilient microprocessor core for dynamic variation tolerance," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 194-208, Jan. 2011.
7. K. Bowman, J. Tschanz, C. Wilkerson, S.-L. Lu, T. Karnik, V. De, and S. Borkar, "Circuit techniques for dynamic variation tolerance," in Proc. 46th ACM/IEEE DAC, Jul. 2009, pp. 4-7.
8. P. Dubey. (2005, Feb.). Recognition, mining and synthesis moves computers to the era of Tera. Technology@Intel Mag., pp. 1-10 [Online]. Available: http://www.larryblakeley.com/Articles/monthly?articles/pradeep?dubey200502.pdf
9. Y.-K. Chen, J. Chhugani, P. Dubey, C. Hughes, D. Kim, S. Kumar, V. Lee, A. Nguyen, and M. Smelyanskiy, "Convergence of recognition, mining, and synthesis workloads and its implications," Proc. IEEE, vol. 96, no. 5, pp. 790-807, May 2008.
10. K. V. Palem, "Computational proof as experiment: Probabilistic algorithms from a thermodynamic perspective," in Verification: Theory and Practice. Berlin, Germany: Springer, 2003, pp. 524-547. (Pubitemid 38318540)
11. S. Thrun, "Probabilistic algorithms in robotics," AI Mag., vol. 21, no. 4, pp. 93-109, 2000. (Pubitemid 32089753)
12. D. Nowroth, I. Polian, and B. Becker, "A study of cognitive resilience in a JPEG compressor," in Proc. IEEE Int. Conf. Dependable Syst. Networks With FTCS DCC DSN, 2008, pp. 32-41.
13. M. Breuer, "Multi-media applications and imprecise computation," in Proc. 8th Euromicro Conf. Digit. Syst. Des., Aug.-Sep. 2005, pp. 2-7. (Pubitemid 44868545)
14. X. Li and D. Yeung, "Exploiting soft computing for increased fault tolerance," in Proc. Workshop Architectural Support Gigascale Integr., 2006.
15. N. Shanbhag, "Reliable and energy-efficient digital signal processing," in Proc. 39th Des. Autom. Conf., 2002, pp. 830-835.
16. V. Wong and M. Horowitz, "Soft error resilience of probabilistic inference applications," in Proc. Workshop Silicon Errors Logic-Syst. Effects, 2006.
17. J. Liu, K.-J. Lin, W.-K. Shih, A.-S. Yu, J.-Y. Chung, and W. Zhao, "Algorithms for scheduling imprecise computations," Computer, vol. 24, no. 5, pp. 58-68, May 1991. (Pubitemid 21717770)
18. L. Leem, H. Cho, J. Bau, Q. A. Jacobson, and S. Mitra, "ERSA: Error resilient system architecture for probabilistic applications," in Proc. Des. Autom. Test Eur. Conf. Exhibit., 2010, pp. 1560-1565.
19. J. D. Davis, C. P. Thacker, and C. Chang. (2009, Apr.). BEE3: Revitalizing computer architecture research. Microsoft Res., Tech. Rep. MSR-TR-2009-45 [Online]. Available: http://research.microsoft.com/pubs/80369/ BEE3 TechReport.pdf
20. D. Koller, N. Friedman, L. Getoor, and B. Taskar, "Graphical models in a nutshell," in An Introduction to Statistical Relational Learning, L. Getoor and B. Taskar, Eds. Cambridge, MA: MIT Press, 2007.
21. G. Bronevetsky and B. de Supinski, "Soft error vulnerability of iterative linear algebra methods," in Proc. 22nd Annu. ICS, 2008, pp. 155-164.
22. R. G. Gallager, Low Density Parity Check Codes (Monograph). Cambridge, MA: MIT Press, 1963.
23. D. Koller and N. Friedman, Probabilistic Graphical Models: Principles and Techniques. Cambridge, MA: MIT Press, 2009.
24. G. Heitz and D. Koller, "Learning spatial context: Using stuff to find things," in Proc. 10th Eur. Conf. Comput. Vis., 2008, pp. 30-43.
25. Y. Li, O. Mutlu, D. S. Gardner, and S. Mitra, "Concurrent autonomous self-test for uncore components in SoCs," in Proc. IEEE VLSI Test Symp., Apr. 2010, pp. 232-237.
26. A. Kumar, J. Rabaey, and K. Ramchandran, "SRAM supply voltage scaling: A reliability perspective," in Proc. ISQED, 2009, pp. 782-787.
27. S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. Kim, "Robust system design with built-in soft-error resilience," Computer, vol. 38, no. 2, pp. 43-52, Feb. 2005. (Pubitemid 40377402)
28. A. Lingamneni, C. Enz, J.-L. Nagel, K. Palem, and C. Piguet, "Energy parsimonious circuit design through probabilistic pruning," in Proc. Des. Autom. Test Eur. Conf. Exhibit., Mar 2011, pp. 1-6.
29. R. Kumar, V. Zyuban, and D. M. Tullsen, "Interconnections in multicore architectures: Understanding mechanisms, overheads and scaling," in Proc. 32nd Annu. ISCA, 2005, pp. 408-419. (Pubitemid 41543458)
30. D. Culler, J. Singh, and A. Gupta, Parallel Computer Architecture: A Hardware/Software Approach (Morgan Kaufmann Series in Computer Architecture and Design), 1st ed. San Francisco, CA: Morgan Kaufmann, 1998.
31. S. Kumar, C. J. Hughes, and A. Nguyen, "Carbon: Architectural support for fine-grained parallelism on chip multiprocessors," in Proc. 34th Annu. Int. Symp. Comput. Architecture, 2007, pp. 162-173. (Pubitemid 47582100)
32. A. Mahmood and E. McCluskey, "Concurrent error detection using watchdog processors: A survey," IEEE Trans. Comput., vol. 37, no. 2, pp. 160-174, Feb. 1988. (Pubitemid 18596597)
33. Cortex-M3 Technical Reference Manual, ARM Ltd., Cambridge, U.K., 2006 [Online]. Available: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/ DDI0337E?cortex?m3?r1p1?trm.pdf
34. I. Nakanishi and Y. Fukui, "A new adaptive convergence factor algorithm with the constant damping parameter," IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. 78, no. 6, pp. 649-655, 1995.
35. Aeroflex Gaisler. Leon3 Processor [Online]. Available: http://www. gaisler.com/cms/index.php?option=com?content&task=view&id=13 &Itemid=53
36. G. A. Reis, J. Chang, and D. I. August, "Automatic instruction-level software-only recovery," IEEE Micro, vol. 27, no. 1, pp. 36-47, Jan. 2007. (Pubitemid 46850886)
37. S. Narayanasamy, A. K. Coskun, and B. Calder, "Transient fault prediction based on anomalies in processor events," in Proc. Des. Autom. Test Eur. Conf. Exhibit., 2007, pp. 1-6.
38. M.-L. Li, P. Ramachandran, S. K. Sahoo, S. V. Adve, V. S. Adve, and Y. Zhou, "Understanding the propagation of hard errors to software and implications for resilient system design," in Proc. 13th Int. Conf. ASPLOS, 2008, pp. 265-276. (Pubitemid 351606091)
39. N. Wang and S. Patel, "Restore: Symptom-based soft error detection in microprocessors," IEEE Trans. Dependable Secure Comput., vol. 3, no. 3, pp. 188-201, Jul.-Sep. 2006. (Pubitemid 44304207)
40. N. J. Wang, A. Mahesri, and S. J. Patel, "Examining ACE analysis reliability estimates using fault-injection," in Proc. 34th Annu. ISCA, 2007, pp. 460-469. (Pubitemid 47582125)
41. T. Sakata, T. Hirotsu, H. Yamada, and T. Kataoka, "A cost-effective dependable microcontroller architecture with instruction-level rollback for soft error recovery," in Proc. 37th Annu. IEEE/IFIP Int. Conf. Dependable Syst. Netw., Jun. 2007, pp. 256-265. (Pubitemid 350080431)
42. P. Ramachandran, P. Kudva, J. Kellington, J. Schumann, and P. Sanda, "Statistical fault injection," in Proc. IEEE Int. Conf. Dependable Syst. Netw. With FTCS DCC DSN, 2008, pp. 122-127.
43. V. Chandra and R. Aitken, "Analytical model for SRAM dynamic writeability degradation due to gate oxide breakdown," in Proc. Des. Autom. Test Eur. Conf. Exhibit., 2011, pp. 1-4.
44. C. Wilkerson, H. Gao, A. Alameldeen, Z. Chishti, M. Khellah, and S.-L. Lu, "Trading off cache capacity for reliability to enable low voltage operation," in Proc. 35th ISCA, Jun. 2008, pp. 203-214.
45. M. Rinard, "Acceptability-oriented computing," in Proc. Companion 18th Annu. ACM SIGPLAN Conf. OOPSLA, 2003, pp. 221-239.
46. J. Meng, S. Chakradhar, and A. Raghunathan, "Best-effort parallel execution framework for recognition and mining applications," in Proc. IEEE Int. Symp. Parallel Distributed Process., May 2009, pp. 1-12.
47. A. Eltawil and F. Kurdahi, "Improving effective yield through error tolerant system design," in Proc. 12th IEEE ICECS, Dec. 2005, pp. 1-4.
48. G. Varatkar, S. Narayanan, N. Shanbhag, and D. Jones, "Sensor networkon-chip," in Proc. Int. Symp. System Chip, Nov. 2007, pp. 1-4.
49. L. Chakrapani, B. Akgul, S. Cheemalavagu, P. Korkmaz, K. Palem, and B. Seshasayee, "Ultraefficient (embedded) SoC architectures based on probabilistic CMOS (PCMOS) technology," in Proc. DATE, vol. 1. Mar. 2006, pp. 1-6.
50. N. Verma, K. H. Lee, and A. Shoeb, "Data-driven approaches for computation in intelligent biomedical devices: A case study of EEG monitoring for chronic seizure detection," J. Low Power Electron. Applicat., vol. 1, no. 1, pp. 150-174, 2011.
51. K. H. Lee, K. J. Jang, S. Mohammed, A. H. Shoeb, and N. Verma, "A data-driven modeling approach to stochastic computation for low-energy biomedical devices," in Proc. 33rd Annu. Int. IEEE EMBS Conf., Aug. 2011.
52. A. Sampson, W. Dietl, E. Fortuna, D. Gnanapragasam, L. Ceze, and D. Grossman, "EnerJ: Approximate data types for safe and general lowpower computation," in Proc. ACM SIGPLAN Conf. PLDI, Jun. 2011, pp. 164-174.
53. K. Pattabiraman, G. Saggese, D. Chen, Z. Kalbarczyk, and R. Iyer, "Automated derivation of application-specific error detectors using dynamic analysis," IEEE Trans. Dependable Secure Comput., vol. 8, no. 5, pp. 640-655, Sep.-Oct. 2011.
54. S. Ghosh, S. Bhunia, and K. Roy, "CRISTA: A new paradigm for lowpower, variation-tolerant, and adaptive circuit synthesis using critical path isolation," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 11, pp. 1947-1956, Nov. 2007.
55. A. B. Kahng, S. Kang, R. Kumar, and J. Sartori, "Designing a processor from the ground up to allow voltage/reliability tradeoffs," in Proc. IEEE 16th Int. HPCA Symp., Jan. 2010, pp. 1-11.
56. K.-H. Huang and J. Abraham, "Algorithm-based fault tolerance for matrix operations," IEEE Trans. Comput., vol. C-33, no. 6, pp. 518-528, Jun. 1984. (Pubitemid 14584528)