Failure analyses of 3D SIP (system-in-package) and WLP (wafer-level package) by finite element methods

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2009, Pages 108-115

  Lau, John ^a   Zheng, Xiaowu ^a   Selvanayagam, Cheryl ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COPPER COMPOUNDS; FAILURE ANALYSIS; FINITE ELEMENT METHOD; INTEGRATED CIRCUITS; PRINTED CIRCUIT BOARDS; SILICA; SILICON WAFERS; SOLDERED JOINTS; SOLDERING ALLOYS; SYSTEM-IN-PACKAGE; THERMAL EXPANSION;

ELECTRONIC PACKAGING; FAILURE LOCATIONS; LEAD-FREE SOLDER JOINT; PRINTED CIRCUIT BOARDS (PCB); STRESS AND STRAIN; THERMAL EXPANSION MISMATCH; WAFER LEVEL PACKAGE; WAFER-LEVEL CHIP SCALE PACKAGES;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 71049186519     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPFA.2009.5232687     Document Type: Conference Paper

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