A consistent deep-level hole trapping model for negative bias temperature instability

IEEE Transactions on Device and Materials Reliability

Volumn 8, Issue 1, 2008, Pages 22-34

  Ang, D S ^a   Wang, S ^a   Du, G A ^a   Hu, Y Z ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

CMOS front end reliability; Direct tunneling; Donorlike interface traps; Hole traps; Negative bias temperature instability (NBTI); Nitrided gate oxide; Oxynitride; Ultrathin gate dielectric

Indexed keywords

ACTIVATION ENERGY; CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE; GATE DIELECTRICS; SILICON; TEMPERATURE MEASUREMENT;

DIRECT TUNNELING; DONORLIKE INTERFACE TRAPS; NEGATIVE BIAS TEMPERATURE INSTABILITY; OXYNITRIDE; ULTRATHIN GATE DIELECTRICS;

HOLE TRAPS;

EID: 40549103184     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2007.912275     Document Type: Article

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