On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET's

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 109-112

  Denais, M ^a,c   Bravaix, A ^c   Huard, V ^b   Parthasarathy, C ^a,c   Ribes, G ^a   Perrier, F ^b   Rey Tauriac, Y ^a   Revil, N ^a  

^a STMICROELECTRONICS   (France)

^b NXP SEMICONDUCTORS   (Netherlands)

^c AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; DEGRADATION; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); HOLE TRAPS; INTEGRAL EQUATIONS; INTEGRATION; MOSFET DEVICES; OXIDES; TRANSCONDUCTANCE; DRAIN CURRENT; NEGATIVE BIAS TEMPERATURE INSTABILITY; THERMODYNAMIC STABILITY; THRESHOLD VOLTAGE;

DRAIN CURRENTS; ELECTRON VALENCE BANDS (EVB); HOLE CURRENTS; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI);

THERMODYNAMIC STABILITY; RECOVERY;

BIAS-TEMPERATURE INSTABILITY; HOLE-TRAPPING; LINEAR DRAIN CURRENT; LOGARITHMIC TIME; NEGATIVE BIAS; PMOSFET'S; TIME DEPENDENCE; TRAPPING/DETRAPPING; ULTRA-THIN GATE OXIDES;

EID: 21644455928     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. "NBTI challenges in PMOSFETs of advanced CMOS technologies" G. La Rosa, International Reliability Physics Symposium, Tutorial, 2003.
2. "Hole trapping effect on methodology for DC and AC Negative Bias Temperature Instability Measurements in PMOS transistors", V. Huard, M. Denais, International Reliability Physics Symposium Proceedings, p. 40, 2004.
3. "Interface traps and oxide traps creation under NBTI and PBTI in advanced CMOS technology with a 2nm gate-oxide" M.Denais, V.Huard, C.Parthasarathy, G.Ribes, F.Perrier, N.Revil, A.Bravaix, Integrated Reliability Workshop proceedings, p. 1, 2003.
4. "Dynamic recovery of negative bias temperature instability in p-type metal-oxide-semiconductor field-effect transistors", M. Ershov, S. Saxena, H. Karbasi, S. Winters, S. Minehane, J. Babcock, R. Lindley, P. Clifton, M. Redford, and A. Shibkov, Applied Physics Letters Vol 83(8), p. 1647, 2003.
5. "Universal recovery behaviour of Negative Bias Temperature Instability", S. Rangan, N. Mielke, E.C.C. Yeh, Internatinal Electron Devices Meeting Technical Digets, p. 341, 2003.
6. JEDEC foundry process qualification guidelines, 2002.
7. "Evidence for hydrogen-related defects during NBTI stress in p-MOSFETs", V. Huard, F. Monsieur, G. Ribes, and S. Bruyere, International Reliability Physics Symposium Proceedings, p. 178, 2003.