Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs

IEEE Transactions on Electron Devices

Volumn 51, Issue 9, 2004, Pages 1371-1379

  Mahapatra, Souvik ^a   Kumar, P Bharath ^a   Alam, M A ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BULK TRAP GENERATION; CLASSICAL REACTION DIFFUSION THEORY; DEVICE DEGRADATION; GATE VOLTAGE; INTERFACE TRAP GENERATION; NEGATIVE BIAS TEMPERATURE INSTABILITY; THIN GATE OXIDE;

DEGRADATION; ELECTRIC POTENTIAL; ELECTRON TRAPS; GATES (TRANSISTOR); HIGH TEMPERATURE EFFECTS; HOLE TRAPS; INTERFACES (MATERIALS); SEMICONDUCTOR DEVICE MODELS; THERMAL DIFFUSION; THERMAL STRESS; THERMODYNAMIC STABILITY;

MOSFET DEVICES;

EID: 4444341905     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.833592     Document Type: Article

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