Interface trap passivation effect in NBTI measurement for p-MOSFET with SiON gate dielectric

IEEE Electron Device Letters

Volumn 26, Issue 10, 2005, Pages 758-760

  Yang, T ^a,b   Shen, C ^a,b   Li, M F ^a,b   Ang, C H ^c   Zhu, C X ^b   Yeo, Y C ^b   Samudra, G ^b   Kwong, D L ^a,d  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c Chartered Semiconductor Manufacturing   (Singapore)

^d The University of Texas at Austin   (United States)

Author keywords

MOSFETs; Negative bias temperature instability (NBTI); Silicon oxynitride (SiON)

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; GATES (TRANSISTOR); HOLE TRAPS; PASSIVATION; SEMICONDUCTING SILICON COMPOUNDS; THRESHOLD VOLTAGE;

NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); SILICON OXYNITRIDE (SION); TRAP PASSIVATION EFFECT;

MOSFET DEVICES;

EID: 27144524994     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.855419     Document Type: Article

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