Negative bias temperature instability: What do we understand?

Microelectronics Reliability

Volumn 47, Issue 6, 2007, Pages 841-852

  Schroder, Dieter K ^a  

^a Arizona State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TRAPS; INTERFACES (MATERIALS); MOSFET DEVICES; THERMAL STRESS; THERMODYNAMIC STABILITY;

CIRCUIT DEGRADATION; ELEVATED TEMPERATURES; INTERFACE TRAPS; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI);

BIAS CURRENTS;

EID: 34247891689     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2006.10.006     Document Type: Article

References (53)

1. Miura Y., and Matukura Y. Investigation of silicon-silicon dioxide interface using MOS structure. Jpn J Appl Phys 5 (1966) 180
2. 2-Si structures under bias. Proc IEEE 54 (1966) 1454
3. Schroder D.K., and Babcock J.A. Negative bias temperature instability: a road to cross in deep submicron silicon semiconductor manufacturing. J Appl Phys 94 (2003) 1-18
4. Stathis J.H., and Zafar S. The negative bias temperature instability in MOS devices: a review. Microelectron Rel 46 (2006) 270-286
5. Huard V., Denais M., and Parthasarathy C. NBTI degradation: from physical mechanisms to modeling. Microelectron Rel 46 (2006) 1-23
6. Alam M.A., and Mahapatra S. A comprehensive model of PMOS NBTI degradation. Microelectron Rel 45 (2005) 71-81
7. Jeppson K.O., and Svensson C.M. Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices. J Appl Phys 48 (1977) 2004-2014
8. 2 interface. Phys Rev 51 (1995) 4218-4230
9. Yang J.B., Chen T.P., Tan S.S., and Chan L. Analytical reaction-diffusion model and the modeling of nitrogen-enhanced negative bias temperature instability. Appl Phys Lett 88 (2006) 172109-1-172109-3
10. 2 interface defects by electron spin resonance. Progr Surf Sci 14 (1983) 201-294
11. 2 interface trap annealing. J Appl Phys 63 (1988) 5776-5793
12. b1 center. Phys Rev Lett 85 (2000) 2773-2776
13. 29Si hyperfine structure. Microelectron Eng 48 (1999) 113-116
14. 2. Phys Rev 57 (1998) 10030-10034
15. Lenahan P, IEEE Rel. Phys. Tutorial Notes, Adv. Rel. Topics, IEEE IRPS, 2002; section 223.
16. b1 "hyperfine spectrum". Appl Phys Lett 76 (2000) 3771-3773
17. 2 interface trap centers. Appl Phys Lett 80 (2002) 1945-1947
18. 2-Si interface states. Appl Phys Lett 8 (1966) 31-33
19. Fleetwood D.M. Long-term annealing study of midgap interface-trap charge neutrality. Appl Phys Lett 60 (1992) 2883-2885
20. Reddy V., Krishnan A.T., Marshall A., Rodriguez J., Natarajan S., Rost Y., et al. Impact of negative bias temperature instability on digital circuit reliability. IEEE Ann Int Rel Symp 40 (2002) 248-254
21. 2 interface during bias-temperature treatment. Solid-State Electron 20 (1977) 891-896
22. Jayaraman R., and Sodini C.G. A 1/f noise technique to extract the oxide-trap density near the conduction band edge of silicon. IEEE Trans Electron Dev 36 (1989) 1773-1782
23. Mitani Y., Nagamine M., Satake H., and Toriumi A. NBTI mechanism in ultra-thin gate dielectric-nitrogen-originated mechanism in SiON. IEEE Int Electron Dev Meet (2002) 509-512
24. Ershov M., Saxena S., Karbasi H., Winters S., Minehane S., Babcock J., et al. Dynamic recovery of negative bias temperature instability in p-type metal-oxide-semiconductor field-effect transistors. Appl Phys Lett 83 (2003) 1647-1649
25. Rangan S., Mielke N., and Yeh E.C.C. Universal recovery behavior of negative bias temperature instability. IEEE Int Electron Dev Meet (2003) 341-344
26. Yang T., Shen C., Li M.F., Ang C.H., Zhu C.X., Yeo Y.C., et al. Interface trap passivation effect in NBTI measurement for p-MOSFET with SiON gate dielectric. IEEE Electron Dev Lett 26 (2006) 758-760
27. Tsujikawa S., Watanabe K., Tsuchiya R., Ohnishi K., and Yugami J. Experimental evidence for the generation of bulk traps by negative bias temperature stress and their impact on the integrity of direct-tunneling gate dielectrics. IEEE VLSI Technol (2003) 139-140
28. Ang D.S. Observation of suppressed interface state relaxation under positive gate biasing of the ultrathin oxynitride gate p-MOSFET subjected to negative-bias temperature stressing. IEEE Electron Dev Lett 27 (2006) 412-415
29. Tsetseris L., Zhou X.J., Fleetwood D.M., Schrimpf R.D., and Pantelides S.T. Physical mechanism of negative-bias temperature instability. Appl Phys Lett 86 (2005) 142103-1-142103-3
30. 2 interface. J Electrochem Soc 125 (1978) 743-746
31. 2/Si interface on reliability issues - negative-bias-temperature instability and Fowler-Nordheim-stress degradation. Appl Phys Lett 81 (2002) 4362-4364
32. Tavel B., Bidaud M., Emonet N., Barge D., Planes N., Brut H., et al. Thin oxynitride solution for digital and mixed-signal 65 nm CMOS platform. IEEE Int Electron Dev Meet (2003) 643-646
33. Ishimaru K., Takayangi M., and Watanabe T. Scaled CMOS with SiON and high k. In: Huff H., Iwai H., and Richter H. (Eds). Silicon materials science and technology (2006), Electrochem. Soc., Pennington, NJ 317-327
34. Mitani Y., Satake H., Nakasaki Y., and Toriumi A. Improvement of charge-to-breakdown distribution by fluorine incorporation into thin gate oxides. IEEE Trans Electron Dev 50 (2003) 2221-2226
35. Ang D.S., and Wang S. On the non-Arrhenius behavior of negative-bias temperature instability. Appl Phys Lett 88 (2006) 093506-1-093506-3
36. 2 and SiON gate dielectrics understood through disorder-controlled kinetics. Microelectron Eng 80 (2005) 122-125
37. Zafar S., Lee B.H., Stathis J., Callegari A., and Ning T. A model for negative bias temperature instability (NBTI) in oxide and high K pFETs. IEEE VLSI Technol (2004) 208-209
38. Kaczer B., Arkhipov V., Degraeve R., Collard N., Groeseneken G., and Goodwin M. Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification. IEEE Ann Int Rel Symp 43 (2005) 381-387
39. Krishnan A.T., Chakravarthi S., Nicollian P., Reddy V., and Krishnan S. Negative bias temperature instability mechanism: the role of molecular hydrogen. Appl Phys Lett 88 (2006) 153518-1-153518-3
40. Varghese D., Saha D., Mahapatra S., Ahmed K., Nouri F., and Alam A. On the dispersive versus Arrhenius temperature activation of NBTI time evolution in plasma nitrided gate oxides: measurements, theory, and implications. IEEE Int Electron Dev Meet (2005) 684-687
41. 2 interface - 5 (2005), Electrochem. Soc., Pennington, NJ 139-146
42. Colman D., Bate R.T., and Mize J.P. Mobility anisotropy and piezoresistance in silicon p-type inversion layers. J Appl Phys 39 (1968) 1923-1931
43. Sato T., Takeishi Y., and Hara H. Effect of crystallographic orientation on mobility, surface state density, and noise in p-type inversion layers on oxidized silicon surfaces. Jpn J Appl Phys 8 (1969) 588-598
44. In: Sze S.M. (Ed). VLSI Technology. 2nd ed. (1988), McGraw-Hill, NY 110
45. Maeda S., Choi J.A., Yang J.H., Jin Y.S., Bae S.K., Kim Y.W., et al. Negative bias temperature instability in triple gate transistors. IEEE Int Reliab Phys Symp 42 (2004) 8-12
46. 2. IEEE VLSI Technol (2005) 128-129
47. Yang M., Chan V.W.C., Chan K.K., Shi L., Fried D.M., Stathis J.H., et al. Hybrid-orientation technology (HOT): opportunities and challenges. IEEE Trans Electron Dev 53 (2006) 965-978
48. Schlünder C., Brederlow R., Wieczorek P., Dahl C., Holz J., Röhner M., et al. Trapping mechanisms in negative bias temperature stressed p-MOSFETs. Microelectron Rel 39 (1999) 821-826
49. Taur Y., and Ning T.H. Fundamentals of Modern VLSI Devices (1998), Cambridge University Press p. 150-1
50. Krishnan A.T., Reddy V., Chakravarthi S., Rodriguez J., John S., and Krishnan S. NBTI impact on transistor and circuit: models, mechanisms, and scaling effects. IEEE Int Electron Dev Meet (2003) 349-352
51. Ghibaudo G. New method for the extraction of MOSFET parameters. Electron Lett 24 (1988) 543-545
52. .
53. Paul B.C., Kang K., Kufluoglu H., Alam M.A., and Roy K. Impact of NBTI on the temporal performance degradation of digital circuits. IEEE Electron Dev Lett 26 (2005) 560-562