Enhancement of BTI degradation in pMOSFETs under high-frequency bipolar gate bias

IEEE Electron Device Letters

Volumn 26, Issue 6, 2005, Pages 387-389

  Zhu, Shiyang ^a   Nakajima, Anri ^a   Ohashi, Takuo ^b   Miyake, Hideharu ^b  

^a HIROSHIMA UNIVERSITY   (Japan)

^b Elpida Memory Inc   (Japan)

Author keywords

Dynamic stress; Negative bias temperature instability (NBTI); pMOSFETs; Recombination; Ultrathin gate oxide

Indexed keywords

ACTIVATION ENERGY; DIELECTRIC MATERIALS; ELECTRON TRAPS; GATES (TRANSISTOR); HOLE TRAPS; SEMICONDUCTING SILICON COMPOUNDS; STRESSES;

DYNAMIC STRESS; HIGH FREQUENCY BIPOLAR GATE; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); ULTRATHIN GATE OXIDE;

MOSFET DEVICES;

EID: 20544437689     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.848075     Document Type: Article

References (14)

1. D. K. Schroder and J. A. Babcock, "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing," J. Appl. Phys., vol. 94, no. 1, pp. 1-18, 2003.
2. G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D. L. Kwong, "Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling," IEEE Electron Device Lett., vol. 23, no. 12, pp. 734-736, Dec. 2002.
3. W. Abadeer and W. Ellis, "Behavior of NBTI under ac dynamic circuit conditions," in Proc. 41st Ann. Int. Rel. Physics Symp., 2003, pp. 17-22.
4. M. Ershov, S. Saxena, H. Karbasi, S. Winters, S. Minehane, J. Babcock, R. Lindley, P. Clifton, M. Redford, and A. Shibkov, "Dynamic recovery of negative bias temperature instability in p-type metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 83, no. 8, pp. 1647-1649, 2003.
5. H. Usui, M. Kanno, and T. Morikawa, "Time and voltage dependence of degradation and recovery under pulsed negative bias temperature stress," in Proc. 41st Ann. Int. Rel. Physics Symp., 2003, pp. 610-611.
6. S. S. Tan, T. P. Chen, C. H. Ang, and L. Chan, "A new waveform-dependent lifetime model for dynamic NBTI in pMOS transistor," in Proc. 41st Ann. Int. Rel. Physics Symp., 2004, pp. 35-39.
7. M. Denais, V. Huard, C. Parthasarathy, G. Ribes, F. Perder, N. Revil, and A. Bravaix, "Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide," IEEE Trans. Device Mater. Reliab., vol. 4, no. 4, pp. 715-722, Apr. 2004.
8. S. Rangan, N. Mielke, and E. C. C. Yeh, "Universal recovery behavior of negative bias temperature instability," in IEDM Tech. Dig., 2003, pp. 341-344.
9. K. Saino, Y. Kato, E. Kitamura, Y. Takaishi, M. Ando, T. Taguwa, T. Kanda, S. Yamada, and T. Sekiguchi, IEDM Tech. Dig., 2003, pp. 415-3418.
10. S. Y. Zhu, A. Nakajima, T. Ohashi, and H. Miyake, "Modified direct-current current-voltage method for interface trap density extraction in metal-oxide-semiconductor field-effect-transistor with tunneling gate dielectrics at high temperature," Jpn. J. Appl. Phys., vol. 44, no. 2, pp. L60-L62, 2005.
11. 2 interface," Phys. Rev. B, vol. 51, no. 7, pp. 4218-4230, 1995.
12. S. Y. Zhu, A. Nakajima, T. Ohashi, and H. Miyake, "Interface trap generation induced by charge pumping current under dynamic oxide field stresses," IEEE Electron Device Lett., vol. 25, no. 3, pp. 216-218, Mar. 2005.
13. T. P. Chen, S. Li, S. Fung, and K. F. Lo, "Interface trap generation by FN injection under dynamic oxide field stress," IEEE Trans. Electron Devices, vol. 45, no. 9, pp. 1920-1926, Sep. 1998.
14. 2 interface and near-interface oxide traps," IEEE Trans. Electron Devices, vol. 41, no. 7, pp. 1213-1216, Jul. 1994.