A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12∼16A) gate oxide

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 74-75

  Chung, Steve S ^a   Chen, S J ^a   Yang, C K ^a   Cheng, S M ^a   Lin, S H ^a   Sheng, Y C ^a   Lin, H S ^a   Hung, K T ^a   Wu, D Y ^a   Yew, T R ^a   Chien, S C ^a   Liou, F T ^a   Wen, Frank ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; ELECTRIC CHARGE; ELECTRON TUNNELING; GATES (TRANSISTOR); INTERFACES (MATERIALS); LEAKAGE CURRENTS;

INTERFACE TRAPS;

CMOS INTEGRATED CIRCUITS;

EID: 0036047591     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)