Low shift and capture power scan tests

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 793-798

  Remersaro, Santiago ^a   Lin, Xijiang ^b   Reddy, Sudhakar M ^a   Pomeranz, Irith ^c   Rajski, Janusz ^b  

^a UNIVERSITY OF IOWA   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

^c PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP TEMPERATURE; CIRCUIT OPERATIONS; CIRCUITS UNDER TEST (CUTS); HOT SPOTTING; INDUSTRIAL CIRCUITS; INTERNATIONAL CONFERENCES; PEAK CURRENTS; POWER DISSIPATIONS; SCAN BASED TESTING; SCAN CHAINS; SCAN TESTING; SUPPLY CURRENTS; SUPPLY VOLTAGES; SWITCHING ACTIVITIES; TEST RESPONSES; TEST SETS; VLSI DESIGNS;

CHAINS; COMPETITION; COMPUTER PROGRAMMING LANGUAGES; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); SWITCHING;

TESTING;

EID: 39749116684     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.101     Document Type: Conference Paper

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