Test vector modification for power reduction during scan testing

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 160-165

  Kajihara, S ^a   Ishida, K ^a   Miyase, K ^a  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Benchmark testing; Circuit faults; Circuit testing; CMOS logic circuits; Electronic equipment testing; Flip flops; Logic testing; Power dissipation; Switching circuits; System testing

Indexed keywords

CHOPPERS (CIRCUITS); ELECTRIC LOSSES; ELECTRONIC EQUIPMENT; ELECTRONIC EQUIPMENT TESTING; ENERGY DISSIPATION; EQUIPMENT TESTING; FLIP FLOP CIRCUITS; OSCILLATORS (ELECTRONIC); SWITCHING CIRCUITS; VLSI CIRCUITS;

BENCHMARK TESTING; CIRCUIT FAULTS; CIRCUIT TESTING; CMOS LOGIC CIRCUITS; LOGIC TESTING; SYSTEM TESTING;

LOGIC CIRCUITS;

EID: 84948410734     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011128     Document Type: Conference Paper

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