Test set compaction algorithms for combinational circuits t

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 8, 2000, Pages 957-963

  Hamzaoglu, Ilker ^a   Patel S, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Combinational circuits; Minimum test set size estimation; Stuck at fault model; Test generation; Test set compaction

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; HEURISTIC METHODS; THEOREM PROVING;

AUTOMATIC TEST PATTERN GENERATION SYSTEM; SINGLE STUCK AT FAULT TEST SET; TEST SET COMPACTION ALGORITHMS;

COMBINATORIAL CIRCUITS;

EID: 0034251319     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.856980     Document Type: Article

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