Design of routing-constrained low power scan chains

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 62-67

  Bonhomme, Y ^a   Girard, P ^a   Guiller, L ^b   Landrault, C ^a   Pravossoudovitch, S ^a   Virazel, A ^a  

^a LIRMM   (France)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOW POWER SCAN CHAINS; POWER CONSUMPTIONS; SCAN-BASED ARCHITECTURES; SYSTEM-ON CHIP (SOC) DESIGN; CLUSTERING PROCESS; CONGESTION PROBLEM; LOW POWER; POWER REDUCTIONS; SCAN CELLS; SCAN CHAIN; SCAN DESIGNS; SCAN TESTING;

COMPUTER AIDED ANALYSIS; COMPUTER SIMULATION; CONSTRAINT THEORY; ELECTRIC POWER UTILIZATION; FORMAL LOGIC; FREQUENCIES; INTEGRATED CIRCUITS; OPTIMIZATION; PROBLEM SOLVING; SCANNING; CLUSTERING ALGORITHMS; EXHIBITIONS;

SYSTEMS ANALYSIS; DESIGN;

EID: 3042513742     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268828     Document Type: Conference Paper

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