Inserting test points to control peak power during scan testing

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2002, Pages 138-146

  Sankaralingam, R ^a   Touba, N A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Built in self test; Circuit faults; Circuit testing; Clocks; Flip flops; Frequency; Power dissipation; Power supplies; Switches; System testing

Indexed keywords

CLOCKS; DEFECTS; DESIGN FOR TESTABILITY; ENERGY DISSIPATION; FAULT TOLERANCE; FLIP FLOP CIRCUITS; HEURISTIC METHODS; HEURISTIC PROGRAMMING; INTEGER PROGRAMMING; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; POWER CONTROL; PROCESS MONITORING; SWITCHES; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; FREQUENCY; POWER SUPPLY; SYSTEM TESTING;

BUILT-IN SELF TEST;

EID: 84948953596     PISSN: 15505774     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2002.1173510     Document Type: Article

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