On identifying don't care inputs of test patterns for combinational circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 364-369

  Kajihara, S ^a   Miyase, K ^a  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; INTEGRATED CIRCUIT TESTING; VECTORS;

FAULT SIMULATION;

COMBINATORIAL CIRCUITS;

EID: 0035215677     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. An experimental chip to evaluate test techniques experiment results
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6. Test set compaction for combinational circuits
7. Cost-effective generation of minimal test sets for stuckat faults in combinational logic circuits
8. ROTCO: A reverse order test compaction technique
9. An algorithm to reduce test application time in full scan designs
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11. Built-in self testing of sequential circuits using precomputed test sets
12. A distributed BIST control scheme for complex VLSI devices
13. Static compaction techniques to control scan vector power dissipation
14. Compact test sets for high defect coverage
15. Delay testing considering power supply noise effects